The concept of system architectural definition at a level of abstraction higher than RTL is a good one. Such methodologies become much more feasible as tools roll out in support. To that end, Synopsys is launching a SystemC simulator to complement its existing SystemC synthesis tool, completing a high-level design flow.
CoCentric System Studio 2002.05 reaches from architectural concept to implementation in hardware and software. It lets designers verify complex systems-on-a-chip (SoCs) with multiple processors, buses, and peripherals early in the design cycle.
Simulation of SystemC-language design representations, including hardware-software cosimulation, goes much faster than at register-transfer level (RTL). Verilog or VHDL circuit elements can be cosimulated along with SystemC representations of the design through cosimulation with VCS and/or Scirocco HDL simulators. Additionally, the VERA testbench automation tool can be brought to bear.
A waveform viewer within the tool resembles the HDL waveform viewer familiar to hardware designers. The viewer can handle SystemC data types as well as HDLs. Simulations are managed using .tcl scripting. The end result is joint verification of algorithms, architectures, hardware, and software at multiple levels of abstraction.
CoCentric System Studio 2002.05 will ship in May. Pricing starts at $26,950 for a one-year license.
Synopsys Inc., (650) 584-5000; www.synopsys.com.