Electronic Design

SystemC Verification Suite Adds Transaction-Level Assertions

One of the greatest benefits of emerging electronic system-level (ESL) methodologies is the ability to exploit techniques such as assertions and transaction-level models. Such techniques are critical in a topdown verification process.

JEDA Technologies' NSCa family of native SystemC assertion-based tools for automation of the verification process were launched in February with support for cycle-level assertions. Now, the company has added transaction-level assertions to the mix, letting system architects and designers create assertion-based checkers at the transaction level.

By lending support for transaction-level assertions to NSCa, JEDA intends to address the missing capabilities in SystemC by adding temporal expressions. The enhancement provides a path from the transaction level to the cycle level, as well as an effective means of ensuring that the system-level requirements are met throughout the design process.

With the addtion of the transactionlevel assertion support, NSCa becomes a native SystemC assertion development and debugging environment for both the transaction- and cycle-level design phases. It enables a top-down process in which the user creates system-level checks used throughout the design and verification process. This executable specification, written as assertions, ensures functional consistency.

NSCa easily integrates into existing SystemC design environments, giving users three ways to write their assertion checks (see the figure). One is to use NSCa assertion macros that can be called directly from within SystemC or C++ functions. A second is to use NSCa's extended C++ syntax. Or third, users may use the tool's language-independent application programming interface (API) to interface a user-specific front end or C+ code base.

NSCa is available immediately. Singleunit pricing for the full assertion development and debug environment starts at $25,000/year.

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JEDA Technologies

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