Electronic Design

SystemVerilog Stands Ready To Take HDLs To System Level

Standards, and their enhancement, are a sign of a technology's maturation. For the Verilog hardware description language (HDL), the latest stage in maturation is SystemVerilog 3.0, which has been approved as an Accellera standard. SystemVerilog extends the language to support architectural and behavioral design and system verification with assertions.

SystemVerilog supports built-in C-language data types, providing a clear translation to and from C to create algorithmic models. It also gives designers an abstract syntax with which to create synthesizable code.

Four procedural assertions have been added to the language for verification enhancement. They let users test Boolean expressions and perform an action based on the value of the expression, or a sequence of expressions, whether true or false.

An Interfaces construct improves modeling, at an abstract level, of the communications between blocks of a digital system. The construct encapsulates communications to facilitate a smooth migration from system-level design to register-transfer level and structural views of the design. Encapsulation of communications also opens the path to reuse of IP.

"SystemVerilog takes Verilog to the next abstraction level," says Dennis Brophy, Accellera's chairman. "The standard marks a dramatic enhancement to Verilog's capability for abstract design, as well as architectural modeling and assertion-based verification," adds Vassilios Gerousis, Accellera's technical committee chairman.

The Language Reference Manual for version 3.0 is available in .pdf format at www.accellera.com. The organization is gathering tool support for the language. Co-Design Automation, developer of the Superlog language and a key technology contributor, offers a SystemVerilog-ready simulator and synthesis front end. Real Intent's Verix formal verification tool will be updated to handle SystemVerilog assertions in the third quarter.

Plans are already afoot for version 3.1, which could see enhancements based on technology donations from Synopsys. Expected in March 2003, Accellera intends to submit version 3.1 to the IEEE for its standards committee's approval.

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