SystemVerilog Supports Verification

To enable an advanced design-for-verification (DFV) methodology, Synopsys has announced broad support for the Accellera SystemVerilog language. By integrating verification throughout the development process, designers can improve quality and productivity. These gains result from advanced verification technologies, such as assertion-based verification, constraint random-test generation, and formal analysis. Coupled with SystemVerilog, the Synopsys DFV technologies create an approach that enables verification throughout the design flow. One of Synopsys' DFV technologies is a hybrid formal RTL verification product called Magellan. It is integrated with Synopsys' Discovery Verification Platform to further strengthen the DFV methodology.