Electronic Design

SystemVerilog Verification Spans Planning To Closure

In design verification, one size does not fit all. What works on the enterprise level may not work for the design team or individual designer, and vice versa. On the heels of its acquisition of Verisity, Cadence has rethought its approach to verification and resegmented its products into a multitiered structure that mimics the old Verisity approach.

The first fruits of that rethinking have arrived in the form of the Incisive Design Team family of products. It was developed for RTL design teams looking to adopt SystemVerilog-based verification that begins with design planning and takes projects through to closure. It features broad SystemVerilog support and tightly coupled methodologies.

The family includes the Incisive Design Team Simulator, enhanced with SystemVerilog testbench extensions, comprehensive SystemVerilog assertion (SVA) support, and integration with the Incisive Design Team Manager. That latter product, an update of the Incisive Verification Manager, runs the gamut of verification-management functions from assertion test planning and tracking to failure and RTL-coverage analysis.

From the Verisity/Axis Systems stable comes the Incisive Design Team Xtreme Server, an acceleration/emulation system that will add SystemVerilog DPI and SVA support in the first quarter of 2006. Lastly, the Incisive Design Team Formal Verifier is optimized for design-team use prior to testbench availability. It also adds SVA extensions.

On the roadmap for Cadence is the Incisive Enterprise family,-an enterprise-level implementation of its verification methodology, and the Incisive HDL family, which is based on a single-kernel simulation architecture and is scaled more for individual usage. Contact Cadence directly for pricing and availability information for Incisive Design Team packages.

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Cadence Design Systems
www.cadence.com

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