Electronic Design

Take A Glimpse At How The EDA Tool Development Cycle Begins

Late in April, it was reported that researchers at IBM's T.J. Watson Research Center in Yorktown Heights, N.Y., had made significant progress in creating arrays of transistors using carbon nanotubes. Although this material technology has been around for about a decade, only recently have strides been made in its application toward electronic circuit design and implementation.

Carbon nanotubes could give Moore's Law enough legs to hold up for quite a while. The tiny cylinders of carbon atoms measure as small as 10 atoms across, or 500 times smaller than silicon-based transistors. The progress made at IBM involves a new batch process for forming large numbers of nanotube transistors. Until now, nanotubes had to be positioned one at a time, or by random chance. That might work in the lab, but it won't permit mass production.

Due to these developments, I started thinking. Eventually, this technology could be made technically and economically viable enough for someone to actually attempt production of a prototype chip. That someone would likely be IBM itself. Nevertheless, when will a technology like carbon nanotubes make the radar screens of EDA tool vendors? Also, what would have to happen for carbon nanotube design tools to take shape?

According to Raul Camposano, chief technology officer and chief information officer at Synopsys Inc., Mountain View, Calif., there's really no way to know that just yet. It's Camposano's job to stay abreast of technology developments such as those made with carbon nanotubes, and he has been watching with interest. From his comments, I gained a bit of insight into the early stages of an EDA tool development cycle.

First, one must consider tools for a new technology from the perspectives of logic design, or what's typically referred to as "front-end" design, and of physical and electrical design, or "back-end" design. In Camposano's view, not much would change in the front-end flow if carbon nanotubes were part of the equation. It stands to reason; logic is logic.

In the back-end flow, things would get interesting. The first item on the agenda would be creating electrical models. In the best-case scenario, this would entail new Spice models for the devices. A worst-case scenario might mean doing modeling in the realm of device physics rather than an electrical equivalent.

Physical design tools would also be required, demanding that design rules be established first. Camposano expects that placement wouldn't work all that differently from how it does today for silicon devices. Routing is another story, though, and it would present some difficult challenges. On average, the nanotube wires used by the IBM research teams in creating transistors are about 1.4 nm in diameter, versus about 500 nm for silicon equivalents.

Generally speaking, the development cycle for EDA tools spans roughly two years from the start to the release of an initial tool. In the case of a long-term technology prospect like carbon nanotubes, there would have to be clear indications that it's manufacturable and economically viable before EDA vendors would undertake tool development. Camposano likens this to silicon-on-insulator, another technology that's just now moving into the mainstream. The semiconductor vendors that took the lead in developing that technology did their own models, shook out the bugs, and then began canvassing EDA vendors about tool flows.

Carbon nanotubes are certainly at least a few years from commercial viability, so they're not even on Synopsys' roadmap yet. But the Raul Camposanos are watching, and when the need arises, they will be ready.

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