Whether you buy third-party IP cores for integration into SoCs, or beg, borrow and/or steal them from other divisions within your own organization, moving IP from place to place and from buyer to seller has been a messy process. In fact, it's messy on both sides of the equation.
IP providers want their cores designed in early. They want to deliver their most recent revisions of their cores with minimal contractual hassles. Perhaps most critically, they want a secure delivery vehicle.
For consumers of IP cores, the issues mesh on contractual issues but diverge elsewhere. Users want and need highly abstract models of the cores they buy for use in ESL design and verification flows. They also want access to the latest IP so that they can try it before they commit to the purchase.
Tenison Design Automation's IP Exchange technology aims to remove many of these barriers to IP delivery and security for sellers and buyers alike. By extending its existing VTOC product, which allows for the creation of C++ (or SystemC) models from RTL code and a testbench, IP Exchange technology is a way to address most, if not all, of the concerns that providers and consumers have regarding the evaluation and reuse of IP.
The IP Exchange technology enables users to not only generate the model, using the existing VTOC capabilities, but to package the models and their content in such a way that it removes many of the legal and contractual issues that can hinder the ability to move IP from buyer to seller or even within different divisions of a large design house.
In essence, this is how it works. Let's say an IP provider has existing RTL code for an IP core, along with an accompanying testbench that it wants to ship to a potential customer. It would run that RTL and testbench through Tenison's VTOC tool, at which point they can decide if they want to generate a straight C++ cycle-callable model or a SystemC model. If it's the latter, VTOC automatically generates a SystemC wrapper for the IP.
It's at this point that IP Exchange technology comes into play. After deciding what kind of model to generate, VTOC now enables the IP provider to invoke controls on the number of licensees and the content of the generated model. The licensing aspects are based on the common Flex LM network license manager used by many software developers to control the use of their software products. IP Exchange enables the IP provider to determine the number of people who may use the core, the duration of use, and the number of locations in which it may be used. It also enables the provider to restrict visibility into hardware registers, protecting sensitive aspects of the IP itself.
The resulting cycle-callable models can then be exported to internal or external users for deployment within system-level simulation flows. Users get native C++ or SystemC hardware models for purposes of verifying their software. It gives design teams the ability to craft new variations of existing designs without access to the RTL associated with new IP they'd like to incorporate. This all happens well in advance of availability of physical hardware-evaluation boards.
For the IP provider, IP Exchange represents a vehicle for IP delivery in a format that largely preempts any possibility of reverse engineering.
At least one major IP provider is supplying IP Exchange technology at this time. ARC has integrated Tenison's VTOC tool into its ARChitect Processor Configurator, which enables ARC's customers to generate cycle-accurate SystemC models of its configurable processors. ARC itself uses the IP Exchange technology to create and distribute a selection of pre-generated models so that customers can evaluate the processors.
VTOC tools equipped with IP Exchange technology are available now; contact Tenison directly for more details on pricing and delivery.
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