Electronic Design

Test Chip Irons Out Wrinkles In 0.13-μm Process

A test chip for researching signal integrity effects in a 0.13-µm process has been taped out. The ATG-SI, a collaboration between UMC, Sunnyvale, Calif., and Synopsys Inc., Mountain View, Calif., contains test structures that permit the study of multiple threshold voltages, inductance effects, and model extraction in UMC's Fusion process technology.

Don MacMillen, vice president of Synopsys' Advanced Technology Group, says Synopsys and UMC will share the data and apply the results. This will allow Synopsys to extend its EDA analysis and simulation tools and UMC to more readily target its deep-submicron processes to high-end SoCs.

The test chip evaluates inductive coupling of global buses routed in the thick copper top layer using both standard driver-receiver pairs and differential on-chip signaling. It contains an expanded matrix of crosstalk capacitive coupling experiments to explore the impact of the timing differential between an aggressor and a victim's switching edges on the overall timing of each path.

Also, the chip is used to evaluate the timing, leakage currents, and switching currents of two blocks with identical functionality: one totally constructed from low-threshold voltage devices and the other synthesized using a combination of low- and high-threshold voltage devices. When design engineers use a high-threshold instead of a low-threshold library, they sacrifice performance for lower leakage power. This chip lets designers assess the tradeoff between performance and lower leakage power to compare simulated effects to real results for a desired outcome.

Find more details at www.umc.com and www.synopsys.com.

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