Test-Vector Generation Draws Major Gains

To design complex ASICs in a timely and cost-effective manner, engineers must incorporate various design-for-test (DFT) methodologies. Early on, for example, they must add boundary as well as internal built-in self-test (BIST) structures and scan circuitry. Once the chip design has been synthesized and is functioning as desired, test-pattern sets can be generated via automatic-test-pattern-generation (ATPG) methods. This latter stage is the domain of Mentor Graphics' FastScan product.

At any stage of the DFT implementation, performance benefits can reap big rewards for million-gate-plus ASIC designs. Taken into this context, it's easy to see the importance of Mentor Graphics' recent announcement. The company has gone public with its achievement of a 10X performance improvement to the FastScan ATPG algorithm. In fact, Mentor claims that it recently achieved a 20% reduction in pattern count on a 17-million-gate design. This reduction was achieved using the enhanced version of FastScan on a networking chip design.

How exactly is FastScan utilized? After scan circuitry has been inserted into a design—using a tool like Mentor's DFTAdvisor—FastScan can be utilized to generate test vectors for the entire design. FastScan supports a full scan methodology. Each flip-flop and latch is converted into scannable flip-flops. These flip-flops can be tested using a combination test-pattern generator.

Unfortunately, scanning every component in a multi-million-gate design is both time consuming and expensive. To simplify matters, the new release of FastScan features ATPG algorithms that optimize compressed pattern generation for very large designs. Further enhancements have been made to the netlist flattener. They improve capacity or memory usage as well as initial design loading and DRC performance. These new algorithms also provide the added benefit of reducing the test-pattern count on most designs.

Even with the dramatic enhancements of FastScan, however, the growing need to improve test quality and at-speed patterns can lead to an overwhelming volume of data. In some cases, test-data volumes actually exceed automatic-test-equipment limits or vendor requirements. Luckily, Mentor's TestKompress and embedded deterministic test (EDT) promise to simplify this data overload.

Clearly, the new version of FastScan boasts many improvements. For example, the user-defined capture feature enables designers to define the allowable clocking sequences for their designs. These clock sequences are then used during ATPG. They ensure that all at-speed tests follow only the legal clock sequences. Capture procedures also can define internally generated clocks. The at-speed test can then use the IC's internal clock sources for a more accurate test.

Another enhancement that's unique to FastScan is an improved fault simulator. This simulator can accurately grade at-speed test coverage. The use of advanced at-speed methodologies is becoming a requirement for designs at 130 nm and below. After all, at-speed testing offers improved detection of speed-related defects.

The creation of at-speed patterns is not an easy task, however. FastScan's approach is to automate the at-speed pattern-generation process (see figure). Meanwhile, the tool's enhanced compression and optimization capabilities significantly reduce the amount of test data that's required for these additional tests. This latest version of the tool suite also promises users up to a tenfold improvement in ATPG performance. Often, such high performance can reduce at-speed pattern-generation run times from days to hours.

At-speed performance also can be provided for memory tests. More and more complex ASIC designs require a large number of small memories or register arrays, which are scattered throughout the layout. As part of the standard package, FastScan's MacroTest capabilities offers a non-intrusive alternative to traditional memory BIST. MacroTest converts block-based test vectors into scan patterns, saving time and effort in developing tests for these types of blocks. By using a design's existing scan circuitry, MacroTest avoids having to add more test logic. As a result, there is no impact on performance.

An enhanced diagnostics capability complements the improved overall performance of this version of FastScan. Scan-based diagnostics play an increasingly crucial role in failure analysis as well as yield improvement and ramp-up. The FastScan Diagnostics were enhanced to support defect diagnostics and isolation for at-speed transition patterns.

All of these FastScan performance improvements are included in the current tool-suite release. This release is available now to current customers at no extra charge.