With functional verification still a huge bottleneck, designers continue to search out ways to speed up the design process. Verisity Design Inc. of Mountain View, Calif., has developed a technology that enables engineers to accelerate their verification by synthesizing testbenches written in the e verification language. These testbenches can then be run on powerful hardware emulation and acceleration systems for a greater performance boost (see the figure).
Verisity's eCelerator synthesis technology synthesizes e code for acceleration. It also lets the company's Specman Elite test-generation software interact directly with the hardware platforms. Constraints allow users to easily indicate which portions of the testbench to target for synthesis. A rich151;yet time-consuming in execution151;subset of e proves to be synthesizable, including bus-functional models, monitors, data and protocol checkers, and more.
Specman Elite interacts with the hardware platforms through a transaction-based interface that links the Specman Elite testbench directly with the synthesized e testbench running in the hardware. This permits Specman Elite to quickly send large amounts of data to the hardware to perform more comprehensive test runs. Users can configure the volume of transactions sent by Specman Elite to the hardware at maximum throughput for regression test suites. Early benchmarking shows a 10× to 6× performance gain.
Initial support is available for the Palladium and CoBALT hardware emulation systems from Quickturn Design Systems, Mentor Graphics' Celaro system, and IKOS Systems' VStation.
For more information about eCelerator and Specman Elite, go to www.verisity.com.