Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all promised by version 5.0 of the VERA testbench automation tool. It also sports tight integration with Synopsys' VCS Verilog simulator as well as a profiler that helps designers identify performance bottlenecks and implement faster testbenches.

A number of optimizations add up to improved overall simulation performance. A direct link between VERA and VCS through the VCS Direct Kernel Interface (DKI) replaces traditional, slower approaches using the Verilog programming language interface (PLI). Simulations with VERA 5.0 and VCS 6.0.1 now run up to twice as fast as earlier releases. The VCS DKI, an optimized direct interface to the simulation kernel, speeds up overall simulation by reducing PLI overhead and enabling VCS simulation optimizations to be applied to the design.

Along with faster overall simulation performance, VERA 5.0 offers real-time access to built-in VCS coverage metrics. This comprehensive capability includes line, toggle, and conditional coverage integrated into the high-speed simulation engine. Also, the simulator's automatic extraction of state machines for state and transition coverage eliminates the need for VERA users to manually define coverage objects. These coverage metrics, along with the functional coverage data available in VERA, let designers aim their verification efforts at the untested portions of the design. This eliminates testbench redundancy and boosts overall verification efficiency.

VERA 5.0 is available now. Developer's licenses start at $23,690 for a one-year technology subscription. Runtime licenses start at $5640 for one year. VCS pricing starts at $20,250 for one-year technology subscription licenses.

Synopsys Inc., (800) 541-7737; www.synopsys.com.

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