Electronic Design

Testbench Platform And Language Take On Analog Signoff

The addition of the VIPer test extension language, improved performance of the binary test database, and availability of electrical verification IP (EVP) for the PCI Express Gen 2 interface standard buoy version 4.0 of Knowlent’s Opal testbench platform. The platform is used for analog validation of high-speed interfaces used in SoC designs implemented in the latest nanometer silicon technologies.

Designers have had access to digital verification IP for years now. But until recently, analog designers have not had the use of analog verification IP. Knowlent provides testbench setups and data collection for each measurement in the PCI Express specification, enabling analog designers to obtain consistent and complete coverage.

For design teams that wish to customize or extend the set of standard tests provided in Knowlent’s pre-built EVP, the VIPer language supports customer test extensions using either the Tcl/Pearl or C programming languages.

The binary database used in Opal to store results of the testbench analyses has been enhanced for quick, in-depth analysis of test results and specifications across hundreds of runs, and gigabytes of Spice simulation data. Users gain at least a 2X performance improvement in the analysis of data in clock-recovery eye diagrams, and random and deterministic jitter. Exploration of variations across design types and environmental conditions also has been enhanced. New custom report generators provides an easy way to share data and results with design team members.

Release 4.0 of the Opal testbench platform is available now. U.S. pricing for time-based licenses starts at $40,000, depending on configuration. Opal is supported on the Sun Solaris, and Redhat Linux operating systems. PCI Express Gen 2 support is available now. Pricing for electrical verification IP depends on the type and maturity of the protocol.

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Knowlent Corp.

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