With the aggressive downscaling of technology nodes and ever-increasing on-chip power consumption, thermal management is becoming a significant design challenge for high-performance microprocessors, integrated network processors, and SoCs. It’s a problem that’s only going worsen, and it needs to be addressed by the EDA industry.
On-chip temperature directly impacts the performance and time to failure of switching devices. Moreover, sub-threshold leakage of CMOS devices depends greatly on the substrate temperature. Substrate temperature rise and interconnect joule heating raises the temperature of interconnect lines. Interconnect reliability and performance degrade with increased metal temperature—because of electromigration and thermo-migration—and increased interconnect metal resistivity, respectively. In addition to the rise of the peak on-chip temperature, various system-level power-management techniques and non-uniform power-distribution policies over the substrate surface result in a non-uniform, on-chip thermal profile and creation of hot spots.
All verification tools for high-performance designs will eventually require an underlying thermal platform to provide the accuracy required for yield, performance, and power signoff. This capability will significantly reduce the time-to-market and cost of the design process. Building such capabilities into an EDA flow is a complicated matter, but it’s necessary to address this emerging challenge for sub-90-nm technology nodes.
What’s needed is an RTL-to-GDSII system containing an embedded thermal-analysis engine that's integrated with various components of the optimization flow. This would allow the system to address the impact of temperature on various on-chip parameters and incorporate effects of non-uniform thermal profiles during the EDA optimization methodologies. The goal is to produce EDA software that provides accuracy as well as scalability to meet next-generation design targets. Such a framework should include thermally aware, full-flow EDA methodologies designed to reduce the impact of on-chip temperature on various circuit parameters. Such methodologies also should consider the non-uniform substrate temperature effects on achieving the design goals without over-optimization.
With such a tool, design teams can analyze thermal profiles and incorporate their effects on various design-optimization flows, specifically the leakage optimization flow that’s more vulnerable to non-uniform on-chip temperatures. Concurrent thermal, timing, power, voltage drop, and EM analysis mechanisms can help measure their inter-relationships, and reflects the impact of device temperature on various aspects of chip performance.
An integrated solution allows for various library-cell-based derating methodologies, including the k-factor derating functions, nonlinear delay models (NLDMs), and scalable polynomial models (SPMs) for delay, power, and leakage. By including a 3D thermal-analysis engine, design teams can consider various packaging and on-chip electro-thermal parameters. Invoking such a tool from the early stages in the physical-synthesis flow allows for thermally aware floorplanning and global placement to minimize the magnitude of non-uniform temperature profiles.
An approach such as this integrates the 3D thermal-analysis engine in the EDA optimization flow and supports characterization capabilities, providing SPDM and SPLM libraries for various process technologies. Consequently, the system is able to evaluate the impact of thermal fluctuations on different characteristics of each cell instance during the timing and power analysis, and to consider those effects dynamically along the physical-synthesis and power-optimization flows.
While temperature-dependent design issues will become dominant factors in resolving signal- and power-integrity issues in future generations of VLSI chips, there’s no need to panic. Effective on-chip thermally aware flows are already available and will continue to improve.