Electronic Design

Timing Checks Go Full Chip

Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform timing calculations. But at nanometer geometries, the gate-level analysis lacks the detail to resolve physical effects that lie at the transistor level.

Also, static gate-level models fail to account for critical timing issues such as changes in cell delay caused by changing operating characteristics. These transistor-level effects are best analyzed using a transistor-level simulation engine. One immediately thinks of Spice and Fast-Spice variants, but Spice engines lack the speed and capacity for the job.

An alternative, Nassda's CRITIC full-chip critical timing simulator, provides the detailed analysis for timing signoff. It performs automatic transistor-level, post-layout analysis of signal and clock nets. On the clock side, it identifies and traces the nets, back-annotates the nets with interconnect RC parasitics, and sets control signals to sensitize the clock paths. It then simulates the clock nets with the Spice model for each cell, including precise fanout loading. Finally, it compares the clock pin delays to those reported by a static analysis tool.

Critical paths are analyzed automatically and are usually chosen from a report generated by a static tool. CRITIC back-annotates post-layout parasitics. It also can automatically include secondary loads to critical paths to account for Miller capacitance and other loading effects. After analysis, the tool sets side-branch values to enable or sensitize the critical paths and creates input patterns for dynamic simulation. CRITIC simulates all paths together at once.

Time-based licenses start at $65,000 with support on numerous platforms.

Nassda Corp.

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