Electronic Design

Timing-Closure Tool Plugs Verification Holes

While static timing analysis remains the go-to technology for verifying timing in complex SoC designs, significant holes remain in typical verification and timing flows. Real Intent’s EnVision TCV, a tool aimed at timing-closure verification, seeks to close those holes by ferreting out timing bugs such as untimed and unverified paths. EnVision TCV includes Real Intent’s Meridian for clock-domain-crossing (CDC) verification and PureTime for timing-exception verification.

Typical functional verification, static timing, and equivalence checking flows don’t cover two sources of errors: clock-domain-crossing signals and exceptions to default timing.

Simulation, emulation, prototyping, or equivalency checking doesn’t verify clock-domain-crossing signals, nor does static timing check them, where in fact they are typically marked as false paths. Meridian (announced by Real Intent in April this year), part of EnVision TCV, is engineered to verify that data traversing asynchronous clock domains on ASIC, SoC, or FPGA devices is received reliably. After quick automatic setup, Meridian formally verifies both the structure and the protocols required for CDC safe design, then pinpoints design problems with an absolute minimum amount of manual sign-off.

PureTime, also part of EnVision TCV, removes the risk of errors in Synopsys Design Constraint (SDC) timing exceptions. PureTime’s automatic processing dramatically improves project schedules when compared to manual review of exceptions. It also provides the accuracy of full sequential analysis. Combinatorial-only solutions can’t analyze multicycle paths, and will erroneously invalidate false paths that full sequential analysis verifies correctly.

EnVision TCV is available now for $97,000. It will be featured in Real Intent’s Booth 5260 at the upcoming 44th Design Automation Conference, June 4-8, San Diego.

Real Intent www.realintent.com

Design Automation Conference Booth 5260

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