Design complexity has reached a point where RTL is no longer a viable starting point for verifying most silicon systems. RTL design optimization and simulation has become so time-consuming that they now threaten product schedules. However, new methodologies like transaction-level modeling (TLM) are emerging to support faster verification and design feedback.
The higher design abstraction level of TLM methodologies enables designers to simulate their systems between 10- and 100-times faster than at RTL. This delivers fast feedback on architectural design decisions and enables earlier hardware/software validation. Although these verification and performance improvements are important, TLM methodologies are about more than verification speed. TLM is also about creating a better design.
TLM provides a greater ability to influence power consumption, performance, and silicon area in a design. As one moves through the design process to lower levels of abstraction, design choices become fixed, reducing the degrees of freedom. Early in the process one can choose what’s in software versus hardware; which bus architecture to use; which processor, etc. But as these decisions are finalized, designers are left with fewer and fewer things that can be adjusted.
Historically, TLM has suffered from two shortcomings: model accuracy and model availability. High-level models inherently lack sufficient accuracy to perform meaningful analysis early in the design process. That’s why most power analysis and optimization actually occurs after synthesis. Today, the focus is on raising the accuracy of TLM models so that meaningful analysis can be performed early in the design process.
In addition, creating TLM models for design refinement can be a labor-intensive process. To solve this, EDA must support a scalable TLM methodology that addresses top-down model creation via high-level synthesis, and bottom-up model creation that leverages existing libraries of RTL.