Electronic Design

Tool Automates Generation Of SystemVerilog Testbenches

The SystemVerilog infrastructure is built out further with Synopsys' introduction of Pioneer-NTB. This testbenchautomation tool delivers native SystemVerilog testbench generation to users of third-party simulators. As a result, verification engineers can adopt a single, standards-based verification infrastructure in mixed-simulation environments.

The efficiency gains are among the chief advantages of using a tool such as Pioneer-NTB with either Synopsys' VCS, Cadence's NC-SIM, or Mentor's ModelSim. Pioneer-NTB can optimize all inputs and compile them natively to run on Sun or Linux workstation farms. One beta user has seen a fivefold performance gain compared to using VCS and Vera testbench generation.

Pioneer-NTB fully supports Synopsys' Reference Verification Methodology, enabling users to quickly adopt best verification practices. It also provides an assertion intellectual-property library to help verify complex protocols. The tool supports all major SystemVerilog verification constructs.

Customers of Synopsys' existing Vera standalone testbenchautomation tool will receive Pioneer-NTB at no charge, giving those Vera users access to SystemVerilog. Pioneer-NTB also supports the OpenVera verification language as well as mixed OpenVera-SystemVerilog environments.

Pricing for Pioneer-NTB starts at $17,150 for a one-year term subscription license. It's available now.

Synopsys
www.synopsys.com

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish