Electronic Design

Tool Corrects Physical IC Designs To Keep Up With Fabs’ Rule Sets

SiFix is a tool that automatically corrects and optimizes physical designs, ensuring that designs are created using the correct rule sets. In the process of shaking out high-end process technologies at 0.13 µm and smaller, semiconductor fabs may subtly alter the design-rule sets that should be used in physical IC design to maximize yields. The result is lots of design-rule checking (DRC) errors and tapeout delays. SiFix minimizes them.

It scans through layout files, using quality and reliability rules to adjust line widths and spacing and increasing strapping in selected nets and segments. When it finds errors and hazards, it fixes them locally, leaving the rest of the physical design as it was. The tool works on full-custom layouts or cell-based designs.

SiFix is available now under time-based licensing starting at $225,000 per year. It runs on Solaris, HP-UX, and Linux platforms.

www.sagantec.com; (510) 360-5200

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