Tool Facilitates Hard-IP Quality Risk Assessments; Collaboration Puts Collected Info Online

Sept. 27, 2007
As the first deliverable in its planned suite of IP-ecosystem tools, the Fabless Semiconductor Association (FSA) has released version 3.0 of its Hard Intellectual Property (IP) Quality Risk Assessment Tool. The tool collects information

As the first deliverable in its planned suite of IP-ecosystem tools, the Fabless Semiconductor Association (FSA) has released version 3.0 of its Hard Intellectual Property (IP) Quality Risk Assessment Tool. The tool collects information about an IP vendor, its design methodology, and the IP family under evaluation to develop a risk assessment profile across seven criteria: IP design, integration, verification, process technology, product documentation, reliability, and test.

The latest version includes several enhancements that improve ease-ofuse and increase communication for integrators and vendors, as well as foundries. For example, a custom questionnaire permits vendors to add questions pertaining to specific IP. The integrator completes those questions and can weight specific factors. This benefit facilitates vendor communication to integrators about a specific IP family.

There's also an "answer verification" feature, which comprises a filter added to the Hard IP summary page so an answer can be verified. With it, vendors and integrators with long-term relationships can add a yes/no confidence level, reflected in a risk profile.

Further, the FSA has collaborated with Chip Estimate Corp. to enable vendors to upload their "risk profiles" to Chip Estimate's IP portal. In addition, Chip Estimate users may request a vendor's risk profiles or ask a vendor to use the risk-assessment tool to complete a profile for their IP.

The Hard-IP Quality Risk Assessment Tool is now freely available. To download version 3.0 and view an online demonstration, visit the FSA Web site.

Chip Estimate Corp.

www.chipestimate.com

Fabless Semiconductor Association

www.fsa.org/IPecosystem

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.

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