A large language gap yawns between chip designers and their foundries. Designers speak of their creations in terms of gain, delays, power, timing, hierarchy, blocks, and errors. At the foundry, however, the discussion is of mask layers and defects. For some time, Mentor Graphics’ Calibre suite has served as an interface between these disparate worlds, putting what designers see in terms that the foundry can understand and vice versa.
Meanwhile, physical verification is becoming an extremely complex undertaking. There are about twice as many rules at the 28-nm node as there were at 90-nm (see the figure). A designer hasn’t been born who can remember them all.
Under these conditions, getting a design to a state in which the fab will ensure manufacturability is a stressful process. It is highly iterative and fraught with long runtimes. Sometimes manual design-rule checking (DRC) fixes introduce new errors. Thus, designers often stop trying to optimize their layout as soon as they see a “clean” DRC result. The alternatives are to take even longer to get a layout done or to hire more layout engineers, both of which have clear business and/or financial ramifications.
Mentor’s response in terms of the Calibre platform is to bring it forward into the design process. This migration really began with last year’s launch of Calibre InRoute, which put the Calibre engine inside the cockpit of the Olympus-SoC router. The next step now comes with the launch of Calibre RealTime, which comprises an integration of Calibre signoff design-rule checking with the SpringSoft Laker custom design environment.
The pairing of Calibre RealTime and Laker is implemented with the OpenAccess runtime model. Together, the tools give layout designers signoff-quality DRC as they make changes, using standard Calibre rule decks. When designers edit a polygon, path, or device placement in Laker, Calibre automatically runs DRC on that change and delivers results immediately without ever leaving the familiar Laker editing cockpit.
It all happens rather quickly, too. In a test of a large 28-nm block, about 3000 checks on 6649 shapes returned results in 0.2 seconds. Add that up across a full standard-cell library and you’re talking about significant time saved over older methodologies, where a similar DRC check might take from 10 to 20 seconds. Designers will gain a lot more time to optimize their work.
When performing routing either manually or automatically in Laker, Calibre detects changes as they are made and finds signoff errors referenced against the golden rule deck that may not be in the internal tech file. As designers instantiate and modify PCells or MCells, Calibre is again automatically invoked to ensure that the cells are placed without creating violations in the layer they are working in or in the layers above or below it.