EE Product News

Tool Optimizes Power Dissipation In ASICs And SOCs

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WattSmith is an architectural-level power optimization tool for power reduction in ASICs and ASSPs for system-on-chip design. The tool replaces lengthy manual design currently required at the register-transfer level (RTL) with no need for specialized low-power expertise, it’s claimed. The tool’s RTL algorithms offer both substantially larger power savings and higher capacity and performance than is available from gate-level and synthesis-based methodologies.The tool uses a modular, agent-based architecture to find power reduction opportunities in large chips. It first builds an expanded RTL database of the design. A suite of WattBots, which are subprograms designed to identify specific power reduction opportunities, then searches this database. The WattBots calculate the available power savings and propose a new design structure while advising on potential tradeoffs, such as area.

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