Electronic Design

Tool Sorts Out The Relationship Between SoC Leakage Current And Temperature

For designs at 90 nm and below, leakage-current management has become a key design challenge. To accurately analyze chip leakage, designers must consider the temperature variation of the chip based on transistor switching current.

Apache's Sahara-PTE offers an integrated means of analyzing the impact of a system-on-a-chip (SoC) design's temperature on leakage, timing, reliability, and voltage drop. Based on 3D thermal models and on the simulation kernel from Apache's RedHawk, Sahara-PTE takes in location-based boundary temperature conditions or extracted package thermal models for fast and accurate power-thermal convergence.

Chip temperature affects the metal resistivity, interconnect self-heating, and voltage drop across the design. Sahara-PTE analyzes the impact on resistance extraction, wire electromigration, and voltage drop. By considering the temperature variation across the chip instead of using constant corner values, Sahara-PTE also provides a much more accurate full-chip analysis of critical paths and clock timing for silicon signoff.

Sahara-PTE will be available this quarter for production use. Annual license pricing starts at $160,000.

Apache Design Solutions

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