Electronic Design

Tool Suite Paves The Path To Network-On-Chip SoCs

As system-on-a-chip (SoC) designs begin migrating down to smaller process geometries, chip sizes stay roughly the same, but their complexity increases tremendously. Signal delays due to wires predominate over gate delays. An on-chip communication crisis calls for new approaches to how IP blocks pass signals between each other.

Last year, Arteris announced its plans for a network-on-chip (NoC) technology based on a globally asynchronous, locally synchronous (GALS) paradigm. That technology is now made tangible by the introduction of tools and IP libraries.

The Danube IP library contains a set of configurable building blocks for managing all on-chip communications between IP cores in an SoC design. It comprises Network Interface Units that provide interfaces to the IP cores, Packet Transport Units, and physical links building up the switch-fabric user-defined topology.

The Danube building blocks use a GALS method to span distance and to cross on-chip clock boundaries. An on-chip protocol "spy" is provided for runtime system-level debug.

With the NoCexplorer exploration tool, users can capture the dataflow requirements of the blocks to be serviced by the NoC. It permits rapid analysis of various NoC topology options to achieve optimal performance and area implementation.

NoCcompiler creates a database of the specific instance of the NoC. It generates various views of the network in HDLs, SystemC, or other standard formats and generates synthesis scripts. Within the tool are capabilities to ensure design consistency across multiple versions, rules checking, and presynthesis area estimation. Its outputs include SystemC cycle-accurate models, synthesizable RTL descriptions, FPGA-optimized outputs, and synthesis scripts.

The Danube NoC IP library is available as licensable IP. The NoCexplorer and NoCcompiler tools have a single-design license list price of $350,000 to $500,000.

Arteris SA
www.arteris.com

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