Tool Supports TDML Standard For Exchange Of Timing Diagrams

Design engineers can quickly evaluate potential components for critical timing constraints and clock speed compatibility with version 5.0 of WaveFormer Pro, which combines a timing diagram analyzer, interactive simulator, and test stimulus generator. It is claimed as the first EDA tool to support the Timing Diagram Markup Language (TDML) standard for exchange of interactive timing diagrams.Users can create, view, design with, and translate TDML timing diagrams into VHDL, Verilog and SPICE. The new version supports 64-bit time values, enabling import and editing of large VCD simulation runs and HP logic analyzer data files, which can be converted into TDML.