Tools vs. designers: the battle line is drawn

Paul Double explains why EDA tool expenditures should not steal budget from analogue designer salaries.

Over the past few years, demand for mixed-signal IC products has climbed dramatically: A recent Fabless Semiconductor Association survey shows that over 40% of the wafers ordered by its members are for mixed-signal design. Despite the growing demand for analogue and mixed-signal devices, semiconductor companies constantly feel the pressure to keep design costs down in order to remain competitive.

Mask fabrication, EDA tools, and design engineers are the major three contributors to overall design cost. Unfortunately, mask-fabrication cost remains high in a market with a very limited number of suppliers. Therefore, semiconductor companies are left with two areas where cost savings can be made—either with the EDA tools or the design engineers themselves.

Digital design engineers have benefited significantly from the automation offered by the EDA tools. Thanks to top-down, synthesis-driven techniques, the design of millions-of-transistors digital chips is achievable with fewer design engineers. EDA tools such as Design Compiler from Synopsys and Cadence's Silicon Ensemble are expensive but are crucial to the digital design flow.

The level of abstraction made possible through Hardware Description Languages (HDLs) also has made highly integrated IC design possible without relying on thousands of digital design engineers (Fig. 1).

The situation is different in analogue design, though. Unlike digital design, it's rare that you can design a reusable algorithm for an analogue application that can be used in different circuit types, as well as for design automation. In analogue design, the skill lies in choosing the right topology for the circuit. This choice depends heavily on the application.

Although the number of transistors in analogue design often is small, the design is still very challenging because it requires detailed understanding of the relationship between on-chip transistors and passive devices. Hence, EDA tools support analogue design engineers but don't replace them. Because a high degree of automation isn't offered in analogue design, effective analogue design tools needn't be expensive.

Big EDA players are proposing unified databases for the different design levels that might hold an advantage. However, it could also cause designers to focus on insignificant issues in the interface between the analogue and digital cores.

Unfortunately, it seems that a full-chip extraction on the GDSII mask level will always be needed to capture parasitics in a design. Some EDA vendors advocate full-chip simulation. Although simulating the whole chip might be useful, it only gives a thumbs-up or thumbs-down. It's handy as a final sanity check, but it won't improve the overall design cycle.

Effective Spice simulation of key blocks in the design is more important. And, effective Spice simulators don't have to be expensive. For example, T-Spice Pro from Tanner EDA is a package that includes a Spice simulator, schematic editor, and a post-processing waveform viewer for under €10,000.

Some smaller EDA companies are promoting synthesisable analogue IP blocks. Though this solution appears to work well for very standard analogue blocks, it is not so efficient for most other analogue blocks. Moreover, such solutions are often expensive. The semiconductor design company ends up buying more IP rather than buying an EDA tool. Hiring an analogue design engineer and buying an analogue design tool will cost you much less than buying a synthesizable analogue IP block, but the IP block advantage is faster time-to-market.

Some tools offer built-in support for custom automation. Mixed-signal designers will often design similar circuits for different ICs, or different cores for the same IC. Examples are phase-locked loops that drive different digital bocks. Laying them out polygon-by-polygon each time is tedious. Fortunately, low-cost tools provide scripting and programming interfaces that are equally as effective as those found in high-end mixed-signal tools.

For example, many IC designers have used the UPI and T-cell programming interfaces in Tanner's L-Edit layout tool to implement libraries of functions that automate the job of generating multi-fingered transistors and other complex shapes, a task that would otherwise take a long time to draw by hand. These "T-cells" are object-oriented and make it possible to build complex hierarchies of circuit elements that can be parametrized and generated quickly before being tuned by the experienced hand of the designer.

Providers of high-end mixed-signal tools have made big claims for the productivity improvements offered by their tools. When you look closely at the mixed-signal design function, it becomes less clear whether features such as on-the-fly design-rule checks will be as effective as promised. Design-rule checks are important, but they're becoming more complex as foundries have to consider the relationship between circuit layouts and the manufacturing quirks of materials such as low-k dielectrics.

The design-rule checks needed to ensure high yield tend to demand the global analysis offered by a back-end tool such as Mentor Graphics' Calibre (Fig. 2). Although on-the-fly design-rule checks may identify local problems, they might not flag more serious violations that take into account cross-chip effects. As a result, you have to question their usefulness to the mixed-signal designer.

Since Mentor Graphics' Calibre is the fastest available DRC tool, it's relatively expensive. The good news is that some EDA companies have taken advantage of Calibre's standardisation in the DRC field and built their own tools to support Calibre. For example, Tanner EDA offers HiPer Verify, a tool that can run Calibre files unmodified with adequate speed for most complex analogue and mixed signal designs. The DRC is run in the background so that designers can view errors while the DRC is still running and edit the layout. The software also accommodates automatic command file updates whenever foundries release revised rule sets.

To summarise, analogue design cannot be de-skilled. The integrated design flows proposed by the largest EDA vendors may look good in theory. However, they're difficult to justify when much lower-cost tools from smaller, specialist vendors achieve the same results at perhaps a tenth of the price, particularly where they offer compatibility with standards such as GDSII and Calibre.

Good analogue designers are rare, so the only way for companies involved with analogue and mixed-signal design to keep their costs under control is to look for lower-cost tools. Such tools would be either as stand-alone solutions or as part of a mixed-signal design flow in which the analogue EDA element is also characterised by dedicated functionality and ease-of-use.

Paul Double is managing director of EDA Solutions.

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