Electronic Design

Transaction-Level Models Are Becoming Easier To Use

Transaction-level modeling (TLM) verification methodologies are propagating down from power users, such as large systems houses and integrated device manufacturers, to the broader design community. As they do so, standards organizations such as the Open Core Protocol International Partnership (OCP-IP) are helping to make TLM methodologies easier to use and ever more powerful.

OCP-IP has released Version 2.1.1 of its TLM Channel specification, as well as a comprehensive methodology white paper that describes the use of TLMs for architectural modeling. The new Channel package offers improved model interoperability. "It's a major step forward in code maturity," says Nokia's Anssi Haverinen, chair of OCP-IP's System-Level Design Group.

Version 2.1.1 improves model interoperability by unifying the way time is modeled in transaction level 1 (TL1). Some TL1 application-programming-interface functions also have been redesigned to ensure interoperability, and new timing interfaces have been added to the TL1 channel for automating the setting of module timing parameters.

"For design-space exploration, a system engineer usually wants to test the effect on performance of the latency of a given IP block," says Haverinen. "We introduced latency parameter values that can be redistributed to different models in system-level runtime. As a result, users no longer need to recompilethe modules if they change their response latency."

The new methodology package also aligns the Open SystemC Initiative's TLM methodology with OCP-IP's. It presents what Haverinen terms a "missing link" for system-on-a-chip (SoC) modeling—an architect's-view use model (see the figure).

The white paper and other information are available to OCPIP-members at the organization's Web site.


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