At each transition to more advanced design and manufacturing technologies, the physical design process has undergone a transformation in breadth of requirements and depth of capability. Now, as the industry moves to deep nanometer technologies at 65 nm and below, conventional approaches for ensuring silicon success are quickly falling behind in their ability to cope with the broadening scope of physical design. The industry now finds itself within a critical transition period toward manufacturing-aware design, requiring an evolution in design methods needed to achieve success in next-generation nanometer ICs.
Each major advance in semiconductor manufacturing technology has presented IC designers with a series of escalating challenges. For years, the greatest challenges in physical design revolved around basic area and electrical requirements. Later, increasingly sophisticated design and manufacturing technologies enabled semiconductor companies to squeeze larger, faster circuits in less area, and IC designers began to find that the back-end design stage began to play a growing role in determining circuit performance. Physical-design-dependent factors such as capacitive coupling and signal integrity that were at most secondary considerations in previous technology generations began to exert a primary influence on performance in mainstream designs. As a result, detailed in-situ and post-layout analysis with parasitic extraction has become compulsory in mainstream signoff flows.
The transition to deep nanometer technologies reprises this same pattern, but at another level of complexity: Manufacturing effects that could largely be ignored above 65 nm dramatically impact performance at 65 nm and below. At these advanced geometries, planarization with chemical mechanical polishing (CMP) can wear down the top of copper wires, which are softer than the surrounding insulating dielectric material. As a result, copper wire thickness—and resulting timing—can vary dramatically, even across a single die. In the past, manufacturing engineers could take steps to mitigate CMP effects through metal fill and slotting, but at deep nanometer geometries, these corrective measures significantly impact circuit performance, due to the increased influence of coupling effects.
Similarly, the need for stronger resolution-enhancement techniques (RET) at these geometries heightens the impact of manufacturing on circuit performance. Even with today’s mainstream geometries, chip structures are smaller than the 193-nm wavelength of light used in silicon lithography, requiring the use of RET technologies, such as optical proximity correction (OPC) and phase shift masks (PSM), to compensate for distortions due to subwavelength diffraction. Although manufacturers typically needed to apply these techniques to only two layers for 180-nm designs, 65-nm design requires correction of all layers—numbering as many as 35 for emerging process technologies. As with CMP, manufacturers could apply these corrections on previous generation designs without fear of impacting performance. For deep nanometer designs, however, the impact of the increasingly comprehensive series of RET corrections requires careful consideration throughout the design process. With newer technologies, engineers can explore the impact of lithography on layout designs, interactively exploring different RET approaches well before tapeout. Here, detailed simulations of lithography effects use process model files that encrypt wafer-process data—providing accurate predictions of lithographic results without compromising confidential manufacturing data. Using this approach, design teams can produce "litho-clean" layouts that reduce the risk of litho-related respins.
Designers now need to approach manufacturing effects with the same concern applied for timing closure—anticipating their impact on timing early in the design cycle and for each block. Design-for-manufacturing (DFM) and design-for-yield (DFY) strategies should be embedded through the entire design flow, including synthesis, placement, routing, and route optimization and finishing. Conversely, design enhancements to compensate for CMP and lithography effects should proceed with clear understanding of design intent such as critical paths to reduce the chance of introducing additional defects due to signal integrity and timing issues.
The trend toward increasing give-and-take between design and manufacturing is further reflected in the nature of the relationship between the semiconductor house and fab. Fabs now augment required rules with optional rules that can help a semiconductor manufacturer achieve the full potential of a new process technology. For designers, the challenge becomes one of balancing traditional objectives with the possible yield improvement gained by exploiting a recommended rule. Because each fab and process node presents different rule sets, that challenge is further complicated by the need to accurately predict circuit performance and yield against an evolving base of manufacturing constraints.
Despite the growing impact of manufacturing on design performance, practical deployment of manufacturing-aware design methods means more than trying to push massive amounts of manufacturing data further upstream. In fact, the most effective approaches will rely on pushing just enough information about manufacturing processes to upstream design stages. This approach will let designers gain the benefit of increased understanding of downstream effects without needing to become experts in downstream technologies. Here, novel modeling techniques will adapt the level of abstraction to deliver a consistent view of a design that’s "just enough" to meet the specialized needs of each stage of IC design. Early in design, these models provide enough detail to speed initial planning and estimation. As designs move closer to manufacturing, however, these models adapt to provide the additional detail needed for more accurate predictions of performance and yield.
To achieve this vision of balanced, manufacturing-aware design flows, designers will need design tools embedded in a single architecture able to moderate the sometimes conflicting demands of design and manufacturing. As the industry deploys newer technologies able to realize this vision of balance between design and manufacturing, semiconductor companies will not just survive the transition to deep nanometer technologies but will achieve the full potential of emerging manufacturing capabilities.