Electronic Design

Try-Before-You-Buy IP Distribution Program Segues Into Implementation

As FPGAs become an increasingly popular implementation platform, their complexity rises accordingly, thanks largely to the proliferation of processor and peripheral IP. A study done by Synplicity last fall found that one-third of all designs implemented on FPGA these days carries at least some IP.

With so many designers implementing IP on FPGAs, it would be useful if they had a vehicle through which they can acquire, evaluate, and integrate that IP. Now, Synplicity is attempting to address this need with its ReadyIP program, billed as the industry’s first and complete universal, encrypted design methodology for FPGA implementation.

The first element of the ReadyIP program is simplified IP access and discovery. A new menu in Synplicity’s Synplify Pro, Synplify Premier, and Certify tools brings up an IP browser called SystemDesigner, which presents users with datasheets on a wide variety of processor and peripheral IP. Links to the IP vendors’ sites for downloading evaluation IP accompany those datasheets.

For IP providers, there’s considerable control over encryption during evaluation. IP is encrypted using a script that specifies the synthesis output method. IP is then packaged in the SPIRIT Consortium’s IP-XACT format. The IP provider fully controls the degree of encryption. Through the SystemDesigner browser, users have various views of the IP, including a library view, and can configure and interconnect the IP they want on their FPGA. The Eclipse-based GUI facilitates reuse of in-house and proprietary IP as well.

The encryption initiative that’s part of the ReadyIP program is based upon Cadence’s donation of the IEEE 1364-2005 specification, which Synplicity built upon in its technology donation to the VSI Alliance in 2006. That technology is now back in the IEEE’s P1735 encryption standard working group.

Tensilica, which was an early partner in the ReadyIP initiative, has agreed to offer a license-free, production-ready version of its Diamond Standard 106Micro processor. The 106Micro is an area-efficient, 32-bit RISC processor that’s based on Tensilica’s Xtensa architecture. Users who download the IP through the ReadyIP program pay no royalties for volumes under 10,000 units.

SYNPLICITY www.synplicity.com

TENSILICA www.tensilica.com

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