Electronic Design

Verification Closure Tool Watches Over Assertions

While assertions and assertion-based verification (ABV) help solve many problems, they also spawn new challenges. How do you write them? Did they cover the entire design? And when is verification complete?

TransEDA's Assertain is billed as a "verification closure-management tool." But it's also a way to derive metrics that can tell users when their verification process is truly complete. Assertain monitors, measures, and manages the verification process in one integrated environment. It brings together rule, protocol, and assertion checking; code and assertion coverage; design and assertion coverability analysis; and test grading and optimization, which is linked to specification coverage.

The tool, which fits seamlessly into established verification flows, uses comprehensive assertion-coverage metrics such as structural, step, and variable coverage. Cross-linked results from assertion coverage and code coverage are combined in a unified database that provides a clear view of verification progress.

In addition, TransEDA's formal engine augments the tool's integrated rule-checking engine with formal verification of design-consistency rules, such as bus contention and high-impedance conditions, finite-state-machine deadlock and livelock, array out-of-bounds, and others.

Available on Solaris and Linux platforms, Assertain starts from $30,000 for a perpetual license.


Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.