In a survey of its own users, Mentor Graphics found that more than half of them spend more than half their time in functional design verification. Of those users, 78% are manually writing directed test sequences. This major timesink cries out for automation. Another 41% use constrained random vector generation to augment those directed tests.
Further, a solid two-thirds of those users surveyed do their verification at the functional level. Only about a third are performing simulation at the architectural level. Why are so many designers stuck at RTL for verification? Why don’t they do more work at the architectural level with transaction-level models, where the simulation runs will be orders of magnitude faster while still answering some important questions about latency, throughput, FIFO use, and more?
The answer lies in some of the broader issues that, to this day, cause many design and verification teams to tread very lightly when it comes to the adoption of electronic system-level (ESL) methodologies. The bridges between ESL and RTL, if they exist at all, are shaky at best. No one wants to write models at ESL that they have to abandon after they’ve moved down to RTL.
Through a two-pronged approach, Mentor Graphics believes it has made a breakthrough in verification efficiency and intelligence. At the same time, the company hopes that it has at last built a sturdy bridge between the ESL and RTL verification worlds.
One aspect of Mentor’s verification improvements, the Questa Multi-view Verification Components (MVCs), is the fruit of its end-of-2006 acquisition of SpiraTech, an ESL startup based in Manchester, U.K., that had some promising technology in mixedabstraction verification. The other improvement, the inFact intelligent testbench automation tool, provides a more intelligent way of constraining testbench generation. When used with the Questa simulator, the pair of breakthrough technologies speeds up verification and drastically boosts verification coverage of system-on-a-chip (SoC) designs.
MAKING MODELS ELASTIC
Mentor’s MVCs are models that can connect to any level of abstraction, from system to gates. This is where the former SpiraTech technology comes into play. “The idea is to write the model once, and then we synthesize adapters to let the components operate on any level of abstraction,” says Robert Hum, vice president and general manager of Mentor’s Design Verification and Test Division. The MVC library, which includes popular communication protocols and buses such as ARM’s AMBA and PCI, can be used starting at ESL. It allows refinement of the IP down through RTL.
Once verification components are available, designers need to create the stimulus to drive the models. Creating test stimulus by hand is one of the most time-consuming steps in the verification flow. Mentor’s answer comes in the form of its inFact intelligent testbench-automation technology, which uses advanced algorithms to synthesize nonrepeating stimulus.
The inFact tool uses Backus- Naur forms to capture the “language” that a port speaks in terms of protocols, legal sequences of events, semantics, and syntax. Then, armed with that knowledge, inFact can set up testbenches with a far more intelligent set of constraints. Those testbenches will generate a cleaner, more efficient set of vectors that should result in greater verification coverage in much less simulation runtime. “You get something that’s more like directed tests without all the labor involved in writing them,” says Hum.
The MVCs and inFact testbench-automation tool come together under the umbrella of Mentor’s Questa functional verification platform (see the figure). The Questa platform now brings together a number of advanced verification technologies, including assertion-based verification (ABV), intelligent testbench automation, MVCs, and coverage-driven verification (CDV), all of which are supported natively by the Questa platform’s assertion engine.
Questa MVCs will be available in the second quarter, while inFact is available now. Pricing starts at $25,000.