EE Product News

Verification Suite Crosses Borders

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The critical verification needs of both design and verification engineers that make up design teams for complex ASICs and SOCs are met by QuickBench Verification Suite 4.0. The suite includes automated validation and functional coverage analysis, concurrency and coordination of system process models, intuitive protocol and timing modeling, and a layered testbench architecture that promotes adoptability and re-use.Release 4.0 incorporates automated validation features to enable the testbench to directly feed information back to the designer. The testbench can report whether the design passed all its tests, list any failures, and can provide statistical information to characterize a given simulation run. Information collectors in the testbench anonymously monitor and store data to make out-of-order results analysis easy. The suite consists of QuickBench Modeler and QuickBench Sequencer. It’s available on HP, Sun and Windows NT platforms.

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