Verification Suite Streamlines IC Design Process

Designed specifically for IC designers using hardware-assisted verification platforms, the Emulation Edge verification suite speeds the functional verification process while optimizing the use of valuable emulation resources. The suite combines four verification tools that work seamlessly together. VN-Check is a configurable hardware-description-language (HDL) checker that identifies bugs or nonsynthesizable constructs prior to emulation. VN-Cover Coverage Analysis is a leading Verilog, VHDL, and dual-language coverage solution. It enables designers to identify and focus test development efforts on the areas of a design that have yet to be fully simulated. Enabling users to gain visibility into the effectiveness of their emulation runs, VN-Cover Emulator produces results that are compatible with VN-Cover. Thus, simulation and emulation coverage can be combined to yield an accurate picture of overall verification completeness. VN-Optimize analyzes test sets from large regression suites and identifies the smallest set of tests that will meet verification goals. All of the tools are bundled within Verification Navigator, an integrated design verification environment that lets IC designers manage the verification process and shorten verification time. Pricing for the Emulation Edge verification suite starts at $50,000 for an annual subscription license.

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