Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout. Synopsys also has added VCS DirectC. This new interface accommodates the use of C/C++ models within a Verilog verification environment.

Coverage metrics are an industry-accepted measure of simulation effectiveness. As a standard part of VCS, designers will now have access to comprehensive built-in coverage analysis, including condition, toggle, line, and finite-state-machine coverage. Using these capabilities built into the VCS engine, design teams can easily determine the quality or "coverage" of their verification tests.

With the latest VCS release, designers only need to compile once to run both simulation and coverage analysis. Due to this single compilation, users will see substantially better compile and run-time performance than with previous point-tool solutions that use the Verilog Programming Language Interface (PLI).

The VCS DirectC interface significantly improves ease-of-use and performance over existing PLI-based methods by enabling designers to directly embed C/C++ functions within their Verilog design description. VCS automatically recognizes these C/C++ function calls and integrates them into the simulation run, in contrast to interfacing with them via manually created PLI files. Furthermore, using this interface eliminates debugging often associated with PLIs. As a result, VCS DirectC users can expect up to a twofold simulation performance improvement over PLI.

"With the VCS DirectC interface, we are able to avoid PLIs, making it easier for us to use C/C++ functions in our system-level verification environment," says Masamichi Kawarabayashi, senior engineering manager of NEC Electronics Inc. "We have seen this interface perform faster compared to equivalent PLIs. Using VCS DirectC, we are able to shorten our overall verification cycle."

"VCS DirectC interface represents a significant improvement in the integration of C/C++ models in a faster Verilog simulation environment," adds Dave Watson, manager of ASIC development at Agile Storage Inc. "We were able to use VCS DirectC immediately in our memory controller and see its performance benefits. We can now focus on the verification effort rather than on developing PLI expertise."

VCS 6.0.1 with built-in coverage and DirectC is now available. VCS pricing begins at $20,250 for a one-year technology subscription license (TSL). A single license enables VCS to run on any supported platform.

Synopsys Inc., 700 East Middlefield Rd., Mountain View, CA 94043; (650) 584-5000; www.synopsys.com.

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