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VHDL Test Bench Generator Sees Revision

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An integrated environment for generating reactive Verilog and VHDL models and test benches from language-independent timing diagrams is embodied in the newly reworked TestBencher Pro v 5.5. The latest revision takes the graphical test bench editing environment of the original software and adds a project management environment for manipulating multiple diagrams and a template-based code generator for customized generation of different types of test benches. The new version is said to enable designers to seamlessly connect their hand-coded and graphically-generated test bench code.In addition, v5.5 supports generation of HDL code constructs that persist over the entire execution time of the test bench, rather than over the execution time of a single timing-diagram transaction. These constructs include: registered logic equations, continuous setup and hold checks, and system-level clock generators. Previously, these commonly used test bench constructs had to be placed in each timing-diagram transaction.

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