Before SoC complexity blew sky-high at deep-submicron nodes, the hardware and software for a system were developed sequentially. That is, software developers didn’t begin their work on an operating system, drivers, and intersystem communications protocol stacks until they had a very solid hardware prototype to base their work on.
However, time-to-market pressures have long since paired with exploding system complexity to make such a scenario entirely unworkable. Doing so invites missed market windows and revenue opportunities. Thus, software development teams needed a means of gaining an early start on their work long before RTL for the hardware is finalized.
Virtual platform technology is the path that gets around this conundrum by taking advantage of a SystemC-based approach to hardware modeling. Virtual platforms solve the issue of having something to co-verify software against, even while the hardware remains fluid and is a moving target. A number of EDA vendors, such as CoWare and Carbon Design Systems, have gone to market with tools that create such virtual platforms, which comprise transaction-level models of the hardware (see the figure). The software teams can then use that abstracted functional version of the hardware to continually verify their software efforts.
As the hardware development process progresses and the hardware is further refined, updated models can be generated and distributed to software development teams. In this manner, hardware and software development can progress together in lockstep.
As a result, the software team is able to stay abreast of changes in the hardware development until they do have initial silicon prototypes from the foundry. At that point, with software that has been updated throughout the hardware design cycle by being run on the virtual platform, final co-verification of the software is a relatively easy process.