One of the hottest design automation trends is silicon virtual prototyping (SVP). SVP can be applied at different levels of the design—system level, register transfer level (RTL), or gate level.
The two main goals of these tools are:
- to ensure that the design is optimized for the application, logically correct, and can be physically implemented at speed
- and to shift the handoff for ASIC designs from the gate level to the RTL level, thereby shortening the time it takes to get to the ASIC vendor.
As expected, the lower the level of the SVP, the more accurate the results. But it takes longer to generate. The higher the level, the larger the impact from information and decisions. By using SVP at a high level of abstraction early in the design process, designers can avoid subsequent timing problems and reduce or eliminate iterations.
If the different forms of SVP realize only a portion of these goals, they will have a significant impact. Barriers to any new tool are primarily the learning curve and the calibration curve—the latter being the time it takes to generate belief in the results. Over the next 12 months, both of these curves will be traversed. I believe we will see SVP become a standard part of the design process for digital design. For analog/mixed-signal designs, SVP, like top-down design and behavioral system-level design, requires a change in design philosophy and approach. Unfortunately, this is coming very, very slowly.
Is SVP a real solution or just another fad that will soon fade away? There's no better place to see and compare tools than the Design Automation Conference (DAC), about to celebrate its 40th anniversary. The conference is a well-known, well-attended forum for the electronic design community to exchange information on products, methodologies, and processes. DAC will be held June 2-6, 2003, at the Anaheim Convention Center in Anaheim, Calif. For more information, call (303) 530-4333, or visit the DAC Web site (www.dac.com) for more details.