EE Product News

Virtual Prototyping Tool Aids System-On-Chip Design

The Pro-Active family has two new versions for embedded system-on-chip IC designers: ArchGen 2.0 model development environment and ASVP Lab 1.1 virtual prototyping tool. ArchGen behavioral modeling environment has added automatic generation of Instruction Set Simulator (ISS) models from the same source as RTL-accurate "C" models, synthesizable RTL models in Verilog or VHDL, and test benches, thereby helping ensure the consistency of all model types and the test bench. It's also added a Verilog to "C" conversion function, enabling the capture of datapath behavior in synthesizable Verilog supporting current industry practice, then automatically converting them to "C" for 1000x enhanced simulation speed, it's claimed. The ASVP Lab tool provides an open environment for constructing Application Specific Virtual Prototypes, used for early functional and performance verification of system ICs, and enabling concurrent software/hardware development.

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