The diverse challenges intrinsic to analog and mixed-signal design make it a complex market to address with EDA tools. Nowhere is this more apparent than in the verification portion of the design cycle. Digital designers have long had a well-supported, top-down verification flow where the tools have evolved to address their needs. On the other hand, analog and custom designers have more of a bottom-up flow, which requires a different set of tools. With the advent of mixed-signal design, both of these flows must be extended or merged to provide a mixed-signal verification flow. A digital designer incorporating analog circuitry will likely have different requirements for the verification environment than an analog designer creating custom analog and mixed-signal blocks. So, taking a one-size-fits-all approach might leave the needs of either designer unanswered.
Looking at the verification task from the digital perspective, there have been recent advances in silicon technology. These have made it possible to craft system-on-a-chip (SoC) designs that combine digital, analog, and embedded memory blocks on a single chip. To boost the chances of first-pass success, a digital verification engineer must typically verify the embedded analog blocks in the full-chip context.
Many considerations that were once thought of as primarily analog or high-performance requirements are now finding their way into traditional digital designs. As a result, there are times when the ability to drop down and simulate at the transistor level for targeted blocks in the full-chip context at times becomes very important. In addition, given the shorter time-to-market and the increased design complexity, designers have to rely heavily on design reuse. This naturally implies that the verification environment needs to handle blocks coming in at different levels of abstraction.
A new design paradigm that supports multilevel, mixed-signal SoC verification is necessary. The ideal solution will easily fit into the existing SoC design flow. It must have the ability to handle multiple levels of abstraction (behavioral, RTL, gates, and transistors) as well as support both digital and analog behavioral modeling. In this case, verifying the connectivity and interaction on block boundaries is the important factor. The entire design can then stay in the familiar Hardware Description Language (HDL) environment, eliminating the need to migrate a predominately digital design into an entirely new verification environment. Moreover, transistor-level blocks can easily be pulled into the full-chip simulation. To achieve this ideal, the verification must tightly integrate best-in-class, proven HDL and transistor-level verification tools.
From an analog point of view, analog and mixed-signal block design is predominately handcrafted, which contrasts with the highly automated SoC design process. The analog designer is the lead engineer, carefully fashioning high-performance analog capabilities that are mixed with a minority of digital circuitry. This calls for a different set of verification requirements than the SoC verification scenario.
Verifying the correct behavior of the analog circuitry at the transistor level is paramount. The designer, though, must be able to create and apply an in-context testbench to drive the block being designed. Creating circuit stimuli from high-level functional specifications is less desirable than being able to use an HDL testbench. The testbench could also be in the form of some digital circuitry. Because this is the block design and debug phase, integrated mixed-signal debug capabilities are very important. The ideal solution is one that easily fits into the existing analog design flow and can accommodate HDL block import.
Once the block design is fully verified, the ultimate goal is to create a high-performance, accurate model of the custom block so that it can be effortlessly incorporated into the SoC flow, greatly streamlining the mixed-signal verification task. Today, however, creating such a model is a labor-intensive and difficult process, requiring high levels of expertise. Consequently, model accuracy and validation is a key challenge.
As more of the design community moves toward analog and mixed-signal designs, pressure for advanced EDA solutions will mount, especially in the critical area of verification. Those who can create solutions addressing the detailed needs of all the various players will flourish. Crafting solutions for the analog and mixed-signal block designer as well as the digital SoC engineer is vital.