From its inception, the holy grail for the design automation industry has been in the analog realm. Digital logic, with its relatively straightforward structures and topologies, has long been the chief beneficiary of the EDA industry’s efforts. Yet compared to the digital domain, automation of analog and mixed-signal design remains lacking. There are some obvious factors at work. Chief among them is the painstakingly hands-on, custom nature of analog design work.
Analog designers are paid to be finicky about their work and simply do not trust efforts to automate their flow, and it’s not just about the threat to their job security. They believe that they can do the job better than an algorithm can. In fact, they’re largely correct in that belief. But there are other, somewhat less obvious issues at work when it comes to the lack of automation in analog/mixedsignal design, particularly in the wireless realm.
CHANGE COMES SLOWLY IN ANALOG
“Every company that is integrating analog/ RF circuitry with digital is slightly different,” says Mar Hershenson, vice president of product development in the Custom Design Business Unit at Magma Design Automation. “The issue is that there are really three design flows: RF, analog, and digital.” For some vendors of RFICs, matters are even more complicated (see “The MEMS Wrinkle”).
“Analog design methodology really hasn’t changed in the last 20 years,” says Hershenson. Primarily, designers rely on editors and a Spice simulator. There’s no parallel in the analog world to the soup-tonuts design creation flow one would find in the digital realm. Thus, it’s entirely feasible for a digital designer to generate 100,000 transistors a week. It’s also entirely feasible for an analog designer to take three months to create 50 transistors.
That’s because the analog portion of the process is largely manual, leaving designers literally to their own devices. Designers must bring a great deal to the party in terms of circuit knowledge and layout skills. Often, they’ll begin with a previous design or some portion thereof, simulating and tweaking until they’re happy with results.
On the layout side, designers typically huddle with mask designers and tell them where to place output devices, how to approach interconnect lengths, and other performance-critical aspects. But little, if any, of this information is captured anywhere.
CO-DESIGN GAINING FAVOR
So for the analog/mixed-signal design team who must integrate digital logic with RF and analog circuitry, where are the bright spots? Most of the advances in analog EDA in the past few years have come on the simulation front. Modern simulators permit cosimulation using Verilog models and full netlists.
“Customers were still reluctant to use it two years ago, but now they do some sort of co-simulation for large chips. It’s the only way to catch simple connectivity mistakes,” says Hershenson. “They’re doing it at a high level but at least they do something.”
One of the latest packages to hit the scene with co-design capabilities is Agilent Technologies’ Advanced Design System 2009 (ADS 2009), the latest revision of Agilent’s flagship design platform. It directly targets the co-simulation sweet spot for wireless consumer electronics such as 4G Long-Term Evolution (LTE) smart phones.
Designing the physical layer of a wireless system means integrating a slew of devices and subsystems that must comply with various specifications, such as LTE, WiMAX, WiMedia, Wireless HD, USB, and so on. In the case of a 4G handset, this integration can be extremely difficult. “Some phone makers spin printed-circuit boards (PCBs) up to 30 times, with teams working in parallel,” says How-Siang Yap, Agilent’s ADS 2009 product manager.
The motivation for co-design in such scenarios is mitigation of the risk of designing various system elements in isolation. A codesign methodology can be the difference between a failed design spin and a successful one. In integrating an RFIC, package, and balun, ADS 2009 was used to find an unexpected resonance at 1.7 GHz (Fig. 1). The three elements were all known-good commodities. But when integrated and co-verified in ADS 2009, this unexpected resonance altered the RFIC response. Catching the problem enabled the integration team to avoid a failed design spin.
Co-design environments like ADS 2009 have to keep up with evolving telecom standards and trends. Both the LTE and WiMAX standards call for multiple-input, multiple-output (MIMO) antenna schemes. To accommodate MIMO technology, ADS 2009 incorporates a companion simulator that accounts for the characteristics of multiple antennas within a handset.
By doing so, the simulator aids in the design of adaptive antenna- matching networks to satisfy LTE system specs. The companion EMPro 3DEM simulator accounts for various phone-human juxtapositions as it verifies that the system meets the LTE specification even as it accounts for health compatibility.
HOW TO BRIDGE THE GAP
Some analog/mixed-signal/RF design teams have dabbled in system-level work, attempting to define their system architecture at high levels of abstraction. But they have found that the transition to a more concrete design representation is challenging.
For Chris Ouslis, vice president of IC technology at Fresco Microchip, the issue has as much to do with how to employ system- level methodologies as with the methodologies themselves. “You can find good people at system level and good people at circuit level, but it’s hard to find people who know how to create verification suites that bridge the gap,” Ouslis says.
Circuits such as an automatic gain-control (AGC) circuit can be particularly difficult to simulate, especially when coupled with the control circuitry for a digital-to-analog converter (DAC), says Ouslis. The workaround is to abstract some of the blocks to hide the true circuit-level operation. The tricky part is balancing simulation granularity against exploding runtimes.
Ouslis is a fan of fast-Spice simulators. “There are good tools from vendors such as Berkeley Design Automation, whose fast-Spice tool is very similar to Cadence’s Spectre Turbo, which in turn is similar to HSpice from Synopsys,” he says. Yet even fast-Spice simulators don’t solve all of his issues. “It’s still such a long simulation that you only do it to ensure things are going in the right direction.”
MODELING STILL A VEXING ISSUE
As every designer knows all too well, even the best simulators are only as good as the models fed into them. “When analog and/or RF circuitry must be combined with digital logic, the challenge is bridging the two,” says Tom Costas, Cadence’s senior product marketing manager for its Virtuoso product line.
“Even if you treat it more as an envelope simulation than a Spice transient model, it’s still a very large analog simulation problem,” says Richard Davis, corecomp architect at Cadence. “There’s a potential for automating that for certain kinds of circuits. We can build a user interface that will characterize the analog circuit and build a behavioral model that behaves similarly. It’s not identical, but it’s close.” Such envelope simulations run faster than a Spice transient
simulation, says Davis, because you don’t simulate all of the carrier cycles. But it still requires the analog designer to know the circuit well and to set up a testbench. The industry, as a whole, needs to move up in abstraction for analog/mixed-signal work, says Costas. Today, a model must be manually created in the Verilog-A modeling language using a text editor. “You have to be able to follow the language syntax,” says Davis. “Typically, analog designers don’t have the expertise to do that.”
Unfortunately, there is still no complete answer to this problem of how to characterize blocks and build behavioral models with at least some automation. Stabs have been attempted at tools of this nature, but the custom nature of analog circuitry makes their use almost as much work as handcoding the models from scratch. “The biggest stumbling block is that the typical RF designer is not a programmer,” says Davis.
PARASITIC EXTRACTION DRIVES MODELING
An important aspect of developing accurate models, of course, is parasitic extraction. Applied Wave Research (AWR) has done a lot of work in this area.
A traditional flow would involve creating a schematic, performing layout and running design-rule checking (DRC) and layout-versus-schematic (LVS) checks, and making sure those respective databases are in sync. Parasitic extraction is then run on the layout. “You can follow that methodology if you wish but we take a different approach,” says Graeme Ritchie, AWR’s Analog Office product manager.”
In AWR’s flow, once you have a schematic, you can begin the process of extraction. “Experience tells you that in some subset of nodes, the parasitics are critical,” Ritchie explains. “Rather than laying out the entire chip or even an entire block, you lay out a few transistors, place and route them, and run parasitic extraction on those interconnects. Those results can then be brought into simulation very early in the design cycle.” The point is to iron out the critical portions before laying out the bulk of the block or chip.
AWR’s ability to approach parasitic extraction in this way is due in part to a unified design database, which tightly links the layout to the schematic. Rather than having two separate databases, the schematic and layout views are simply different views of the unified object-oriented database. “The connectivity is inherently known as soon as you create it in the schematic,” says Ritchie.
In the AWR flow, if only one net is being extracted, the user has a choice of extraction engines depending on the operating frequency and application (Fig. 2). AWR offers three engines: OEA Net-An, an RLCK extractor; AWR ACE, a microwavefrequency extractor; and Axiem, a full 3D planar electromagnetic solver. The choice of extraction engine is as simple as highlighting a net in the schematic and telling the environment which one to use.
“It’s a speed/accuracy tradeoff,” says Ritchie. It’s best to save the 3D EM solver for gnarly things like spiral inductors. But you can choose the right technology for a given application.”
SIMULATORS STILL IMPROVING
Once the modeling issues are overcome, the good news is that simulation technology continues to improve. For example, Synopsys recently released its CustomSim circuit simulator, which combines three simulation engines under a single shared license (NanoSim, HSIM, and XA). The result is high-throughput co-simulation with the VCS digital simulator as well as a unified analog/mixed-signal simulation environment with sufficient power and speed for large designs.
Most modern circuit simulators fall into one of two broad categories. There are traditional Spice-based engines such as HSpice, which are highly accurate, “golden” simulator, and there are various flavors of “fast-Spice” simulators, which trade off some accuracy for speed.
“Some circuits, such as PLLs (phaselocked loops) with digital control logic, fall into the gap between these two extremes,” says Graham Etchells, director of product marketing at Synopsys’ AMS Group.
Synopsys tweaked the three engines to cover these types of circuits that fall between those requiring the accuracy of full Spice and those that do not. Fast transient simulations of PLLs, charge pumps, and regulators run forever in Spice. Synopsys tuned its XA engine to address fast transient simulations, achieving a good compromise between accuracy and speed.
The CustomSim environment also performs what Synopsys terms “native circuit checking,” a process intended to find design errors before tapeout (Fig. 3). “Before launching simulation, we run a battery of electrical rule checks as well as static and dynamic checks on the block or full chip,” says Etchells.
In keeping with the trend of late, Synopsys has also reconfigured the entire Discovery 2009 verification platform to take advantage of multicore hardware architectures. Some of the engines have been rewritten to deliver speedups of up to four times on four-core machines.
In addition, the CustomSim circuit simulator is adept at transistor-level, lowpower verification tasks. It can put a chip or block through its power-up/down sequences, perform static checks for leakage paths, ensure that MT-CMOS devices are correctly configured for safe operation, and determine the impact of IR drop on performance.