Electronic Design

Writing Testbenches Using SystemVerilog

By Janick Bergeron, Synopsys Inc.ISBN: 0387292217

Survey hardware design teams and you’ll find that the old saw is true: anywhere from 60% to 80% of the overall design cycle is consumed not with design itself, but rather with the nerve-wracking process of determining just what has been designed and whether it functions in accordance with the original design specification. SoC designs are getting larger and verification engineers are struggling to keep up.

The SystemVerilog language, or IEEE Std 1800-2005, was conceived to address this issue. It’s chock-full of extensions and enhancements that are intended to tackle the verification bottleneck. But taking advantage of the language’s most powerful verification constructs is not necessarily for the faint of heart. EDA vendors, looking to ease adoption of SystemVerilog, have put a good deal of effort into verification methodology manuals and other means of guiding verification teams through the thicket of the language’s intricacies.

One of the world’s leading SystemVerilog experts, Synopsys Scientist Janick Bergeron, has done his part in the education effort through a number of books on SystemVerilog. His latest, Writing Testbenches Using SystemVerilog, is aimed at getting readers with a basic understanding of VHDL, Verilog, OpenVera, or e started on using the advanced verification constructs in SystemVerilog.

The book gives readers an introduction to all elements of a modern, scalable verification environment. It also gives them a foundation for adopting the advanced verification methodology detailed in the Synopsys/ARM Verification Methodology Manual, to which Bergeron was a key contributor.

This book is highly recommended for anyone contemplating a move to SystemVerilog, and particularly for those wanting to go beyond simple assertions to take on the language’s more rigorous verification features. Bergeron talks you through the basics of verification; outlines some of the technologies that come into play such as linting, simulation, code coverage, functional coverage, assertions, issue tracking, and others; and goes on to detail the topic of verification planning.

Later chapters dig into how to approach high-level modeling and the ins and outs of data abstraction. For those of you who passed on it in school, object-oriented programming is covered (without which it’s difficult to really take advantage of SystemVerilog). After covering the basics of stimulus and response, Bergeron then settles into the meat of this volume, which explains how to put together a testbench that will completely exercise your design. A final chapter covers simulation management, including transaction-level modeling and regression testing.


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