Electronic Design

Yield Diagnostics Tool Seeks To Apply Test Data

There's a large and growing gap between IC lithography wavelengths and the feature sizes of the ICs themselves. The result is more lithography-driven process variability, which has surpassed random-particle defects as the predominant yield-loss mechanism in nanometer ICs.

One way to address these problems is to move more information from the manufacturing-test operations to the design side. Mentor Graphics' YieldAssist tool aims to do just that. In the process, it quickly and accurately identifies and isolates yield-limiting defects. Information is taken directly from manufacturing test results to facilitate yield learning and eliminate lengthy manual analysis.

YieldAssist allows manufacturers to harvest information on failing devices from wafer sort and then use that data to identify both systematic and random defects. It also provides the needed link back into the design process for improving design for manufacturability as well as for adaptively improving the quality of manufacturing test itself and reducing defect-per-million rates.

The tool addresses three key areas concerning yield learning and monitoring: high-quality test, effective defect isolation, and rapid high-volume diagnosis. It relies on manufacturing tests created with Mentor's TestKompress or FastScan ATPG tools. A link to Mentor's Calibre results-viewing environment lets users view suspected defects in the physical design layout view to further isolate problems down to a physical feature. High-volume diagnosis is accomplished in production environments by directly reading failure logs from compressed test patterns.

YieldAssist is available now. Pricing starts at $126,000/year for a term-based license.

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Mentor Graphics

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