Electronic Design

Yield-Modeling Platform Readies ICs For Tapeout

IC yields are becoming much more limited by process technology than by the IC designs themselves. And with each process generation, optimal yields have fallen progressively lower. Some experts expect that, without intervention, yields at 65 nm likely will be in the single digits. Thus, a design-manufacturing gap has opened and is widening with each process generation.

Ponte Solutions believes the way to come at this problem is through visibility into yield problems at the design stage. To that end, the startup is planning its initial products around three core capabilities: a comprehensive unified yield-modeling platform, high-capacity data processing, and robust yield analysis.

Traditional design-for-yield methodologies have relied on rule-based, design-independent systems. Such rule-based approaches reflect neither process variations nor design specifics. Ponte's approach will be based on statistical yield models derived from its unified yield-modeling platform, which enables strong correlation with foundry results.

The unified models cover random and systematic defect types as well as catastrophic and parametric failures. They'll enable an expandable framework that supports third-party yield models.

Ponte's yield-analysis technology will handle custom and cell-based structures for accurate, full-chip analysis. It also will enable design-content-specific analysis for various defects in addition to "what-if" analysis scenarios. It's orders of magnitude faster than rule-based systems as well.

Ponte Solutions, which was formerly known as EZ-CAD, expects to launch its line of design-for-yield software tools by the end of 2005.

See associated figure

Ponte Solutions

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.