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Q&A with Verific’s Rob Dekker on Parsers, Elaborators

Sept. 17, 2014
Technology Editor Bill Wong talks with Rob Dekker about EDA, synthesis, parsers, and elaborators and why focusing on core competency is a recipe for success.
Rob Dekker is CTO and Founder of Verific Design Automation.

Rob Dekker’s involvement in logic synthesis technology spans more than 20 years. He’s developed a thriving business selling register-transfer-level (RTL) parsers and elaborators to companies offering commercial EDA tools and electronics companies implementing or upgrading their design flows. I spoke with him about trends in the electronics area.

Wong: What are RTL parsers and elaborators?

Dekker: They are software to prepare SystemVerilog and VHDL descriptions for processing by EDA tools. The VHDL, Verilog, or SystemVerilog input consists of RTL source code. The parser creates a machine-readable representation of the source called a parse tree; the analyzer checks that it is all in good order; and the elaborator creates a netlist. Downstream tools such as simulators, formal verification, and FPGA synthesis then use that parse tree or netlist representation for their specific application.

Wong: Why are companies attracted to working with Verific and not building their own elaborators or parsers?

Dekker: We have a 15-year history of building these parsers that have been used in many production environments. Our licensees range from EDA to ASIC and FPGA companies, both large and small, that can implement our software on top of their applications, enabling them to develop design tools more quickly and at a lower cost. Some applications are used as in-house tools and others are shipped as part of a commercial EDA product. Over the years, more than 60,000 copies have been shipped by over 90 companies.

I can point to many benefits a company gets from using software like ours instead of developing its own. Of course, faster time-to-market is an obvious reason. We estimate companies can save 12 to 36 months by outsourcing this aspect of software development to Verific, especially when our software is production-proven, and we are known to provide good customer support. A company also doesn’t need to recruit a team to develop the software and another team to test and debug it. Human resources can be a huge consideration for startups and established companies alike, and it can be a challenge to recruit engineers with just the right experience and skill set.

Focus is important for a startup, too, but every company needs to be conscious of its core competency to be strategic and differentiated. For licensees of software such as ours, they aren’t wasting time and talent on non-strategic HDL software.

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Wong: How hard are they to build? How long would it take for an engineering team to build an elaborator or parser?

Dekker: As with any complicated piece of software, the more skilled the engineer, the faster and less bug-prone the tool. When I started Verific and began building the software, it took me nine months to write the code, test it, and debug it, and this was the third synthesis tool I built from scratch. Someone attempting to build a Verilog front end could do it in under a year, but the tool will be immature and could require bug-fix releases and workarounds. It’s also a year that the engineering team could be focused on another project more in line with the company’s core competency. And then, we are not yet talking about VHDL let alone SystemVerilog.

Wong: Which HDL is more prevalent today –– VHDL, Verilog, or SystemVerilog?

Dekker: We keep a close tally on how our parsers and elaborators are used, and have a fairly accurate take on which HDL fares better than the others.

Of all aggregate licenses, including non-active licenses, 97 % licenses Verilog or SystemVerilog, and 76 % licenses VHDL. Of all currently active licenses, 98 % licenses Verilog or SystemVerilog, and 75 % licenses VHDL. Although VHDL is not as popular as Verilog or SystemVerilog, it is being used.

Wong: Does one work better on some applications than others?

Dekker: The question might be where are VHDL, Verilog, and SystemVerilog being used, because one is more widely used over the other in different regions of the world. For example, VHDL is popular in Europe with the telecommunications companies, and in the U.S. with defense contractors because VHDL was funded by the U.S. Department of Defense in the 1980s.

Conversely, Verilog was a language designed by Gateway Design Automation in the 1980s to drive its commercial and well-used simulator Verilog. When the company was acquired by Cadence Design Systems, it placed the Verilog HDL into the public domain and it became an industry standard. That spawned a cottage industry of startup companies producing Verilog HDL-based simulators, many of which are still in use.

SystemVerilog was initially called SUPERLOG, and was developed by a startup company called Co-Design to enhance Verilog. When Co-Design was acquired by Synopsys, it too was placed in the public domain through standards group Accellera and has since developed a large following.

Wong: What overall technology trends are you seeing in the electronics area?

Dekker: I can identify two trends.

Electronic companies are relying more than ever on third parties to supply specific pieces of semiconductor intellectual property (IP). The move to add more third-party blocks of IP on a system-on-a-chip (SoC) design is unmistakable, and we’re seeing many new and innovative IP companies. More pieces of IP on a chip equates to more complexity and the need for more verification.

Differentiation also is prompting electronic companies to look for ways to streamline and customize their design flows. They are picking and choosing EDA tools for various steps in the flow and are not relying on a single vendor to supply the complete tool suite. Instead, they build internal flows and add in proprietary steps. If that requires parsing SystemVerilog or VHDL, they come to us.

In 1999, Rob Dekker formed Verific, a provider of hardware-description-language (HDL) source code software. Today, Dekker and a team of dedicated engineers develop parsers and elaborators for SystemVerilog, Verilog, and VHDL that have been used as the front-end software for synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications.

Prior to founding Verific, Dekker was a software developer, manager, and director at Exemplar Logic, now part of Mentor Graphics. He was the architect and a primary developer of Leonardo, synthesis software used by field-programmable-gate-array (FPGA) designers. Dekker started his career with Philips Research in the Netherlands, where he worked on the testability of VLSI circuits. He graduated from Delft University of Technology, the Netherlands, with a Master of Science degree in electrical engineering.

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