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White Papers: Custom ADC at CERN | 6 SERDES Design & Verification Challenges | More

Sponsored by Mentor Graphics

Mentor GraphicsElectronic Design is dedicated to keeping design engineers informed of the latest advancements in the engineering community. As such, we thought you would have interest in these resources from Mentor Graphics.

Analog-to-Digital Converter Performance Signoff

Analog-to-digital converters (ADCs) are key building blocks in wireless communications and many other applications. This white paper describes ADC performance signoff with AFS transient noise at a leading provider of 3G, 4G and next-generation wireless technologies. Highlights include:

•    ADC noise analysis challenges
•    Description of previous ADC noise analysis methodology
•    Details on new signoff methodology

High-Performance ADC Simulation at the CERN Large Hadron Collider

The ATLAS Experiment at the CERN Large Hadron Collider required the design of a custom ADC. The ADC developed for this application is a dual-channel 12-bit ADC test chip, in which each channel consists of four pipeline stages to resolve the four most significant bits, followed by an 8-bit successive-approximation-register (SAR) ADC. Learn about the extensive chip simulations performed during the design phase that led to high confidence of success at the tape-out stage in this white paper.

Overcoming SerDes Design and Simulation Challenges - Part 1

The concept of taking a parallel stream of data, converting it to a serial stream, and then converting back to a parallel stream sounds easy. However, the simulation of Serializer/Deserializer (SerDes) devices presents unique simulation challenges. Read this new white paper to learn about overcoming 6 SerDes design and simulation challenges.

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