Powerelectronics 1048 Sepic Buck Eq1 0

SEPIC + Buck = Improved Converter Performance

Sept. 27, 2011
A new high-performance power supply topology creates highly efficient, ultra-dense, low EMI switching converters.

Solus Power Topology™ developed by CUI Inc. of Tualatin, OR, combines a single-ended primary-inductor converter (SEPIC) with a buck converter to form a SEPIC-fed buck converter. This patented topology allows for the development of a wide range of next generation ac-dc and dc-dc power conversion platforms.

The ability to reduce power losses is an important aspect of the Solus Power Topology. Increased efficiency is accomplished by reducing both the conduction and switching losses at several critical points within the converter circuit. The loss reduction is so significant that it can increase the output current by 40% for a given power supply package size. Conversely, the loss reduction enables increased efficiency by several percent for ìgreenî designs for a given output current and package size when compared to the traditional buck topology.

As shown in Fig. 1, the Solus Power Topology includes one magnetic component, one control switch and two commutation switches that are optimally controlled by pulse-width modulation (PWM). The magnetic component consists of four inductively-coupled inductors wound on the same core. This translates to a level simplicity on par with a traditional buck converter.

The Solus topology incorporates the characteristics in demand for high performance power conversion:

  • High power density
  • High efficiency for ìgreenerî systems
  • Fast transient response
  • Low EMI

The Solus topology reduces conduction losses by channeling the operating currents into multiple paths. Q1SB is a high-side switch for both the SEPIC and buck operation. Q2B is a low-side switch for buck operation. Q2S is part of the SEPIC operation. When the input current enters the converter, the topology branches that input into multiple paths, with each path carrying a lower current. This reduces conduction losses, which are significantly less than standard buck converter losses. The reduced current imposed on the MOSFETs allows the circuit to sustain lower losses for a given set of devices.

Lower Voltage and Current Stress

The multiple-current paths, characteristic in the Solus topology, also reduce the voltage stress on components by nearly 50%. This opens the possibility that, for a given voltage conversion, the design may use lower voltage MOSFETs and capacitors than the standard buck converter. Also, this allows substitution of lower RDS(ON) MOSFETs for a given package size.

VDS, the drain to source voltage stresses, of the three MOSFETs in Fig. 1 are:

NQB2060 product specifications:
  • VIN = 36 to 60 Vdc
  • VOUT = 12 Vdc
  • IOUT(max) = 60 A over full input voltage range
  • POUT = 720 W
  • Form factor = 58.4 x 36.8 x 12.2 mm (2.3 x 1.45 x 0.48 inches)
  • Efficiency (η): (VIN = 48 Vdc and VOUT = 12 Vdc)
  • @ Full load > 95%
  • @ Peak (approx. 60% load) = 96%
  • Over full input voltage range > 95%
  • Available in both first generation DOSA (2 output pins) and second generation DOSA (4 output pins) configurations.

The above VDS relationships are affected by the four inductively-coupled inductors. For example, T1A affects the VDS of Q1SB and Q2B that make up a synchronous buck converter. T1B affects the VDS of Q2S.

Fig. 2(a) shows the power loss exhibited by a typical synchronous buck converter. The commutation network in Solus produces fast switching and changes VDS of Q1SB from VIN + VOUT to 0.5(VIN + VOUT).

ISOLUS = ID, the Q1SB drain current. Also, as shown in Fig. 2(b):

Where:

D = Duty cycle

Thus, the high-side MOSFET (Q1SB) reduces its turn-on loss about 75% compared to the traditional buck converter.

Lower Switching Losses

This topology is ideally suited for implementing the gate-charge-extraction (GCE) circuit, which has the ability to turn off the silicon MOSFET channel in less than a nanosecond. Fig. 3 shows the Solus turn-off waveforms for the high side switch (HSS). The oscilloscope capture in Fig. 3 shows the voltage and current waveforms for HSS turn-off. In Fig. 4, the red curve shows the instantaneous power during turn-off, which is approximately 50 W peak and lasts 6.4 nsec for a total power loss at 200 kHz of a negligible 68 mW.

CUI Pursues Innovative Technology

A technology company, CUI is dedicated to the development, commercialization, and distribution of innovative electro-mechanical products. Over the past 20 years, CUI has expanded its presence worldwide in power conversion, interconnect, motion control, and accoustic technologies.

CUI Inc, recently reached a statement of cooperation with Ericsson under which it will develop and market multi-source, digital Point-of-Load (POL) power solutions based on the Ericsson footprints and designs. The agreement concerns Ericssonís current BMR46X platform and plans for its expansion. CUI will initially develop and bring to market a solution that is pin and function compatible with the BMR46X platform under CUI’s Novum Advanced Power product line. Novum digital non-isolated POL modules allow power design engineers to realize better energy efficiencies, more compact designs, and improved time-to-market compared to traditional analog technology. The initial efforts by CUI will be within the 12A to 50A range.

Fig. 5 demonstrates the total high-side transistor switching loss for the Solus converter and the traditional standard buck converter. As the output-to-intput voltage step-down ratio, M, moves from 0.100, to 0.250, to 0.660, the Solus losses are improved by 91%, 88%, and 70%, respectively. Thus, the Solus topology is ideal for wide-conversion-ratio POL applications.

At increased switching frequencies, these improvements become even more compelling. The higher the switching frequency you can produce, the higher the power density, if converter efficiency is held to a reasonable level. If we assume that identical switching devices are used in a buck and Solus design, the Solus Power Topology has the potential to reduce the switching losses by over 90%. This allows the Solus converter to operate at a higher switching frequency without sacrificing very much efficiency, permitting benchmark power density at very reasonable levels of efficiency.

As described, the Solus topology accomplishes performance improvements with novel conversion methods, not higher performance components or sophisticated control. However, any improvements obtained by other factors will further enhance Solusí performance.

Input current to the Solus topology is almost straight dc with only slight ripple, so you can reduce the input capacitors value up to 95%. This input characteristic also reduces EMI caused by input current ripple.

720 W Isolated DC-DC Quarter Brick

The first product based on the Solus topology is the NQB Series, an isolated dc-dc quarter brick (Fig. 6). As part of CUI’s Novum Advanced Power™ portfolio, the 720 W intermediate bus converter will initially support an input range of 36-60 V with an output of 12 V and provide an efficiency greater than 96% (For more product details, see the sidebar: NQB2060 product specifications). The NQB product will eventually support a wider input range as well as an output of 9.6 V.

Additional features include options for DOSA first or second generation footprint compatibility, remote on/off, and load share capability. The NQB Series addresses the trend of rising power requirements and efficiency demands in telecom systems and data centers. It provides a 445 W/in3 power density over its full 36-60 V input range.

The Solus Power Topology can be used with both isolated and non-isolated dc-dc power supply designs. It is particularly suited for non-isolated dc-dc point-of-load (POL) power supplies, due to its ability to provide a wider duty cycle, D, for given output to input voltage ratio, M.

Future Developments

The Solus Power Topology maintains its effectiveness independent of its control method. It can operate with analog voltage mode control, analog current mode control, and various digital control profiles. That opens the door for implementing this topology in a variety of power supply product platforms.

Since the topology can operate very efficiently over a wide voltage range, designers can substantially reduce the amount of the bulk hold-up capacitance, reducing the total cost of the power supply. To this end, the company is working with Ericsson to develop point-of-load power solutions (see sidebar: CUI Pursues Innovative Technology).

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About the Author

Sam Davis

Sam Davis was the editor-in-chief of Power Electronics Technology magazine and website that is now part of Electronic Design. He has 18 years experience in electronic engineering design and management, six years in public relations and 25 years as a trade press editor. He holds a BSEE from Case-Western Reserve University, and did graduate work at the same school and UCLA. Sam was the editor for PCIM, the predecessor to Power Electronics Technology, from 1984 to 2004. His engineering experience includes circuit and system design for Litton Systems, Bunker-Ramo, Rocketdyne, and Clevite Corporation.. Design tasks included analog circuits, display systems, power supplies, underwater ordnance systems, and test systems. He also served as a program manager for a Litton Systems Navy program.

Sam is the author of Computer Data Displays, a book published by Prentice-Hall in the U.S. and Japan in 1969. He is also a recipient of the Jesse Neal Award for trade press editorial excellence, and has one patent for naval ship construction that simplifies electronic system integration.

You can also check out his Power Electronics blog

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