Powerelectronics 1422 Buck Eq 1

Innovative Design Shrinks Buck Converter Size, Cuts External Parts Count

May 31, 2012
A four-member 4A to 15A buck converter family approaches DC-DC PowerSOC capability by integrating the majority of its components, including the inductor and separate power MOSFET chip in a single QFN package.

Enpirion’s EN2300 family of highly integrated, buck converter modules includes an integrated controller, power MOSFET switches and inductor housed in a standard QFN IC package. These internal components and minimal external components combine to produce a complete dc-dc converter whose size and performance improves on traditional discrete dc-dc converter solutions.

The power IC operates from 0.9 to 1.3 MHz, which allows smaller size capacitors and inductors. It uses a voltage mode PWM topology that achieves ±2% output voltage accuracy over line/load and temperature.

MOSFET switches employ a proprietary high-speed transistor structure implemented in a 0.18µ LDMOS process that yields a figure of merit (on-resistance × gate charge) of 20 that is a 40% improvement over alternative LDMOS, 73% versus VDMOS, and 30% versus GaN. In addition, these MOSFETs’ minimize switching losses when operating in the MHz region.

Inductor size is minimized by using a special core material and packaging. It works efficiently in the MHz range and its dc resistance is minimized to reduce losses.

This multi-chip and inductor platform is standard for the four different versions listed in Table 1. Fig. 1 illustrates the internal construction of a typical family member. Each version has a synchronous rectifier with N- and P-channel power MOSFETs that handle the rated continuous load current. All EN2300 devices achieve up to 95% efficiency. Overall efficiency depends on VIN, VOUT, and the switching frequency.

Fig. 2 is a typical application circuit. The EN2300 family uses a type IV compensation network whose components are mostly internal. This requires an external phase lead capacitor (CA) and a resistor (RCA) to stabilize the loop. You can optimize the compensation network to achieve either the smallest size or highest performance by selecting the recommended CA and RCA values for various PVIN and VOUT applications.

You can also optimize total compensation to obtain either low output ripple or small solution size. This results in a wide loop bandwidth and excellent load transient performance for most applications. The EN2300 family also provides the capability to modify the control loop response to customize it for a specific application.

Each family member has an internal linear regulator that converts PVIN to 3.0V. The linear regulator output is available at the AVINO pin.

The circuit that sets the output voltage is a external resistor divider network consisting of RA and RB, as shown in the following:

Round RA up to closest standard value higher than the calculated value.

VFB = 0.75 (nominal)

External Components

The majority of external components for the EN2300 family are those found in most traditional dc-dc converter IC solutions, such as the setting the output voltage, current limit, compensation, and switching frequency as well as input, output, and soft-start capacitors. The EN2300 family only needs about six additional resistors and capacitors, which is far less than older generation converters. External components required for the Fig. 2 application include:

  • 1µF, X5R/X7R, capacitor between AVINO and AGND
  • 0.1µF, X5R/X7R, capacitor between AVIN and AGND
  • 0.1 µF capacitor from PG to BTMP
  • 1µF capacitor from VDDB (internal linear regulator output) to BGND
  • RVB between AVINO and VDDB; recommended RVB = 4.75kΩ
  • CIN, input capacitor 22µF (1206)
  • COUT, Output capacitor 2 x 22µF (0805)
  • Soft-start capacitor 47 nF (Placed between the SS pin and AGND; it ramps the output voltage gradually upon start-up. Typical soft-start rise time is ~3.2ms.)
  • Phase lead capacitor (CA) and a resistor (RCA) stabilize the loop.
  • Resistors RA and RB adjust the output voltage
  • Resistor (RFS) from FADJ to AGND adjusts the switching frequency
  • Resistor (RCLX) from RCLX to AGND sets overcurrent protection
  • Resistor (RPOK) is a pull-up resistor for POK (Power O.K.)

The ENABLE pin can either enable normal operation or shut down the device. Asserting a logic high enables the converter for normal operation and also starts a normal soft-start. A logic low disables the converter, powering it down in a controlled manner. The ENABLE signal has to be low for at least 8ms to allow the device to be re-enabled.

Frequency Synchronization

Using the S_IN pin, you can phase-lock the switching frequency to an external clock source that moves unwanted beat frequencies out of band. (S_IN is a digital Input pin; it accepts either an input clock to phase lock the internal switching frequency or an S_OUT signal from another member of this family.) An activity detector recognizes the presence of an external clock signal and automatically phase-locks the internal oscillator to this external clock. Phase-lock occurs as long as the input clock frequency is in the range of 0.9MHz to 1.3MHz. With no clock present, the device free runs at the internal oscillator’s frequency. A 3KΩ RFS resistor from FADJ to AGND sets the nominal switching frequency to 1MHz. You can optimize efficiency for various PVIN/VOUT combinations by using RFS to adjust the switching frequency. To reduce EMI, you can employ spread spectrum operation by sweeping the external clock frequency between 0.9MHz and 1.3MHz at repetition rates of up to 10 kHz.

A POK (power OK) signal indicates that the converter output voltage is within its specified range. This open drain output requires a pull up resistor to AVIN or a similar voltage. Typically, a 100kΩ or lower resistance is used as the pull-up resistor. The POK signal is a logic high when the output voltage is above 90% of VOUT. If the output voltage goes outside this range, the POK output goes low.

Protection Features

One of the EN2300 family protection features is programmable over-current protection (OCP), achieved by sensing the current flowing through an internal sense P-channel MOSFET that is part of its synchronous rectifier. When the sensed current exceeds the current limit, both power MOSFETs are turned off for the rest of the switching cycle. Removing the over-current condition re-enables PWM operation. If the over-current condition persists, the circuit continues to protect the load.

If the OCP circuit trips consistently in normal operation, the device enters a hiccup mode in which the device is disabled for a short while and restarted with a normal soft-start. The hiccup time is approximately 32ms. This cycle can continue indefinitely as long as the over-current condition persists.

You program the OCP trip point with the RCLX resistor from RCLX to AGND (Fig. 2). The value of the resistor connected between RCLX and AGND determines the OCP trip point. Generally, the higher the RCLX value, the higher the current limit threshold. Leaving the RCLX pin open eliminates current limit protection.

Thermal protection consists of shutdown with hysteresis that disables operation if the junction temperature exceeds approximately 150ºC. When the junction temperature drops by approximately 20ºC after a thermal shutdown event, the converter re-starts with a normal soft-start.

Under-voltage lockout (UVLO) protection ensures that the converter will not start switching until the input voltage is above the specified minimum voltage. Hysteresis, input de-glitch and output leading edge blanking ensures high noise immunity and prevents false UVLO triggers.

Capacitor Selection

The EN2300 products require very little input capacitance. As an example, both the EN2340 and EN2360 require only a 22µF/1206 input capacitor. You can use low-cost, low-ESR ceramic capacitors with an X5R or X7R dielectric for this purpose. To provide high frequency decoupling, some applications may require lower value capacitors in parallel with the larger capacitors.

Output ripple voltage is determined by the aggregate output capacitor impedance, consisting of capacitive reactance, effective series resistance, ESR, and effective series inductance, ESL reactance. Placing output capacitors in parallel reduces the impedance and provides lower ripple voltage.

Thermal effects are important power supply design considerations that cannot be avoided. Whenever there are power losses in a system, the heat generated by the power dissipation must be addressed. For example, the 4A Enpirion EN2340QI converter is housed in an 8x11x3mm 68-pin QFN package. The QFN package has copper lead frames with exposed thermal pads that should be soldered directly on to a copper ground pad on the printed circuit board (PCB) for additional heat sinking.

The recommended maximum junction temperature for continuous operation is 125°C. Continuous operation above 125°C may reduce long-term reliability. The device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 150°C. The EN2340QI is guaranteed to support the full 4A output current up to 85°C ambient temperature. The maximum ambient temperature the device can reach is 98°C given the input and output conditions.

High power load applications can be handled by paralleling the EN23F0 device. Up to four devices can be paralleled. Fig. 3 shows a typical configuration for paralleling two EN23F0QI, 15A devices. This configuration can handle 90% of the total rating of the devices. That is, two 15A devices in parallel can safely handle a 27A load.


The layout in Fig. 4 shows the critical components and top layer traces for minimum footprint with ENABLE tied to AVIN. Alternate circuit configurations and other low-power pins need to be connected and routed according to the specific application.

Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EN2300 package as possible. They should be connected to the device with very short and wide traces. The +V and GND traces between the capacitors and the EN2300 family should be as close to each other as possible, so that the gap between the two nodes is minimized, even under the capacitors.

The PGND connections for the input and output capacitors on layer 1 must have a slit between them to provide separation between input and output current loops.

The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. The thermal pad underneath the component must be connected to the system ground plane through as many vias as possible.

Use multiple small vias to connect ground terminal of the input capacitor and output capacitors to the system ground plane. Put these vias along the edge of the GND copper closest to the +V copper. These vias connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input and output current loops. If vias cannot be placed under the capacitors, then place them on both sides of the slit in the top layer PGND copper.

AVIN is the power supply for the small-signal control circuits. It should be connected to the input voltage at a quiet point. In the VOUT, sense point should be just after the last output filter capacitor. Keep the sense trace short in order to avoid noise coupling into the node.

Keep RA, CA, RB, and RCA close to the VFB pin. Keep the trace to this pin as short as possible. Whenever possible, connect RB directly to the AGND pins.

Solid Tantalum Capacitors

Solid electrolyte capacitors contain manganese dioxide on a tantalum pentoxide dielectric layer. Next, this tantalum pellet is coated with graphite, followed by a layer of metallic silver — providing a solderable surface between the pellet and the can in which it will be enclosed. The pellet, with lead wire and header attached, is inserted into the can where the pellet is held in place by solder. After assembly, the capacitors are tested and inspected for reliability.

Another variation of the solid electrolyte tantalum capacitor encases the element in epoxy resins. It offers excellent reliability and high stability for consumer and commercial electronics with the added feature of low cost. Surface-mount designs of solid tantalum capacitors use lead frames or lead frameless designs.

Solid electrolyte designs are used in applications where their very small size for a given unit of capacitance is important. They typically will withstand up to about 10% of the rated dc working voltage in a reverse direction. Also important are their good low-temperature performance characteristics and freedom from corrosive electrolytes.

Solid tantalum capacitors have no limitation on shelf life. The dielectric is stable, and no reformation is required. The only factors that affect future performance of the capacitors are high humidity conditions and extreme storage temperatures. Solderability of solder coated surfaces may be affected by storage in excess of one year under temperatures greater than 40°C or humidities greater than 80% relative humidity. Terminations should be checked for solderability in the event an oxidation develops on the solder plating.

Wet electrolyte types have the following advantages over the solid system:

  • Supports higher voltage dielectrics — voltage ratings to 125 V are available for wet tantalum, but 50 V is the maximum for dry tantalum
  • Better self-healing characteristics requiring less voltage derating — recommended voltage derating is typically 50% for solid tantalum but only 20% for wet tantalum, enabling higher application capacitance use.
  • Construction supports dielectric formation for larger anodes than available for tantalum chip, allowing CV combinations to 2200 uF/25 V or 1000 uF/60 V — typically 10× the CV available in discrete tantalum chip.

Fig. 3 compares the wet and solid tantalum capacitors in terms of capacitance/voltage.

LTC3109 Features:

  • Operates from inputs as low as ±30mV
  • Only ±1°C needed across TEG to produce adequate current to harvest energy
  • Proprietary auto-polarity architecture
  • Complete energy harvesting power management system
  • Selectable VOUT of 2.35V, 3.3V, 4.1V or 5V
  • 2.2V, 5mA LDO
  • Logic-controlled output
  • Energy storage capability for operation during power interruption
  • Power Good indicator
  • Uses standard compact step-up transformers
  • Small, 20-Pin (4mm × 4mm) QFN or SSOP packages

LTC3109 Features:

  • Operates from inputs as low as ±30mV
  • Only ±1°C needed across TEG to produce adequate current to harvest energy
  • Proprietary auto-polarity architecture
  • Complete energy harvesting power management system
  • Selectable VOUT of 2.35V, 3.3V, 4.1V or 5V
  • 2.2V, 5mA LDO
  • Logic-controlled output
  • Energy storage capability for operation during power interruption
  • Power Good indicator
  • Uses standard compact step-up transformers
  • Small, 20-Pin (4mm × 4mm) QFN or SSOP packages

Related Articles:

Buck-Converter Design Demystified

Power Conversion Synthesis Part 1: Buck Converter Design

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Exploiting Integrated Planar Magnetics

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