Using A Supercapacitor To Improve Linear Regulator Performance

Where V_reg and V_p are the regulated output and the input voltages, respectively.

Usually in a linear regulator configuration, most of the energy is dissipated across the pass-element or the series power semiconductor. Introducing a voltage dropper in series with the pass element will make the dissipation across the pass element lower.

Placing a resistor in series with the pass element as shown in Fig.  6.9 would move some of the energy to the resistor, but this will not improve the overall ETEE.

For this purpose, the ideal voltage dropper element which can be used in the series path is an energy storing element, such as a capacitor or an inductor. If an inductor voltage is used as a voltage dropper, current through the inductor cannot be a constant. A capacitor is the matching candidate as a series dropper element, but in such a case if the capacitance is very small it will block the circuit quickly, stopping the current in a negligible period of time. As discussed in Section 6.1, an extremely large ideal capacitor can be logically used as a lossless dropper in a linear regulator in the series path. The fundamental concept of choosing a supercapacitor as the series dropper element is as follows.

The voltage change (dv) across a very large capacitance C such as a supercapacitor is very small when a finite charge (or discharge) current i(t) flows during a finite time t

A large capacitor, such as a supercapacitor (with negligible ESR value) with a DC voltage can be used as a voltage dropper in the series path, then the effect of the voltage change (dv) due to charging the capacitor for a finite amount of time, can be neglected in terms of the operational principles applicable to that particular circuit. For example, when a large capacitor is connected in series to a circuit for a finite time, the capacitor will not act as a blocking element to that circuit due to charging during that time. Based on this simple principle, using a single supercapacitor or an array of supercapacitors in the series path to store and release the energy, the supercapacitor based efficiency improvement technique suitable for linear regulators was developed (Kularatna and Fernando, 2009,2011).

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Fig. 6.10 illustrates the concept: a supercapacitor C_SC is placed in series with the input of the LDO. Since the series capacitor is large (of the order of farads), it will pass current as it charges for a reasonable period of time. Based on this simple principle, a single supercapacitor can cyclically store and release energy. As per Fig. 6.10 in the first phase of the operation, the supercapacitor is charged from the unregulated power supply. When the value of LDO input voltage, V_in drops to the minimum allowable voltage V_{min_in} the operation is switched to the next phase. In this phase, disconnecting the unregulated power supply, the supercapacitor is connected in parallel with the input of the LDO as shown in Fig.  6.10(b), to release the stored energy in the supercapacitor.

Assuming the initial voltage across the supercapacitor (C_SC)isV_SC(0) after charging for a period t, the instantaneous voltage across the capacitor V_SC is given by,

Where I_L is the load current entering the capacitor from the unregulated power supply. (We can assume that the load acts as a constant-current sink, and that the bypass current from the LDO to ground can be neglected.)

The unregulated source voltage V_p, equals the sum of the supercapacitor voltage and the LDO input voltage,

The supercapacitor charges until V_in reaches V_{min_in} while the voltage across the capacitor reaches Vp - V_{min_in}  at the end of the charging time. In order to discharge this supercapacitor at the next stage down to V_{min_in}, the criterion Vp - V_{min_in} be satisfied. This creates the condition V_p > 2V_{min_in}.

At the end of the charging cycle, the stored energy can be released as shown in Fig. 6.10(b). Discharging continues until the LDO input voltage drops back to V_{min_in} satisfying the following equation,

The circuit draws power from the unregulated input only during half the time of its operating period: during the supercapacitor charging phase, the supercapacitor draws current from the unregulated supply, whereas during the discharging, the supercapacitor delivers power to the LDO keeping the unregulated power supply disconnected from the system.

Considering the charge balance of the supercapacitor during the charge-discharge cycle,

Where t_ch and t_dch are charge time and discharge time, respectively. This gives,

So that the average input current drawn from the unregulated power supply is,

Assuming that the capacitors and switching elements are ideal and neglecting the power consumed by the control circuits, the approximate end-to end efficiency is given by,

The discussion above applies to a practical DC-DC converter such as 12-to-5 V converter, where maximum ETEE possible is 5/12 of 100% which is approximately 42%. In a practical implementation, a supercapacitor can be used with a DC voltage between 6.7 (12-5.3 V) and 5.3 V for case with a commercial LDO chip with a minimum input voltage such as 5.3 V at the regulation. As we see from Eqn (6.11) maximum efficiency achievable is 84%. Practical values of 79-81% were achieved in preliminary proof of concept projects (Kularatna and Fernando, 2009; Kularatna et al.,2010). More discussion on this subject will be found in section 6.6. In general, the practical scenario is, the supercap keeps charging above its average DC voltage within the cycle, in the series mode, and later the supercap releases its charge until it reaches a minimum voltage required for the operation of the LDO, keeping the DC rail disconnected.

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As shown in Fig. 6.11 an array of n ideal series supercapacitors,C_SC each, is placed in series with the input of the LDO. This configuration is applicable to a SCALDO regulator, when it satisfies the criterion V_p > 2V_{min_in} . Basically, this is the extended version of the single supercapacitor, n=1 case. The number of supercapacitors, n, can be determined using the following formula

As the equivalent capacitance of the series capacitor array is large (in the order of farads), it will pass current as it charges for a reasonable period of time. As per Fig. 6.11 (a) in the first phase of the operation, the series capacitor array is charged until the value of the LDO input voltage, Vin is dropped down to its minimum possible input voltage, V_{min_in} .

Assuming the initial voltage across a supercapacitor (C_SC)isV_SC(0), after charging for a period t, the instantaneous voltage across the capacitor V_SC is given by,

Where I_L is the load current entering each capacitor from the power supply during the

charging process assuming the ground pin current is negligible.

The voltage across a single capacitor at the end of the charging is,

At the end of this phase, the array of supercapacitors is connected to the input of the LDO as an array of parallel capacitor as shown in Fig. (b) to release the stored energy. This discharging process continues until the LDO input voltage drops back to V_{min_in}.

The circuit draws power from the unregulated supply during the supercapacitor charging phase (t_ch), whereas during the discharge phase (t_dch) the supercapacitor delivers power to the LDO keeping the unregulated power supply disconnected from the system.

Considering the charge balance of a single capacitor during charge-discharge cycles,

which gives,

The average input current taken from the unregulated power supply is,

Assuming that the capacitors and switching elements are ideal and neglecting the power consumed by control circuits, approximate ETEE for this configuration is given by,

6.4.2 Parallel to series SC array

As shown in Fig. 6.12(a) an array of n ideal parallel supercapacitors C_SC each, is placed in the input of the LDO. This is applicable to a SCALDO regulator

When V_p > 2V_{min_in} .The number of supercapacitors, n, can be determined using the following formula.

As the resultant of the parallel capacitor array is large (in the order of farads), it will pass current as it charges for a reasonable period of time. As per Fig.  6.12(a) in the first phase of the operation, the parallel capacitor array is charged until the value of the LDO input voltage, V_in drops to V_{min_in}.

Assuming the initial voltage across a supercapacitor (C_SC)isV_SC(0), after charging for a period t, the instantaneous voltage across each capacitor V_SC is given by,

Where IL/n is the portion of load current entering each capacitor from the power supply during the charging process assuming the ground pin current is negligible. The voltage across a single capacitor at the end of charging is,

As shown in Fig.  6.12(b), in the next phase of operation, using an array of series capacitors, the stored energy is released until the LDO input voltage drops back to V_{min_in}.

Considering the charge balance of a single capacitor during charge discharge cycles,

which gives,

Therefore, the average input current drawn from the unregulated power supply is,

Similar to V_p > 2V_{min_in} case, under ideal conditions, the approximate ETEE is given by,

Table 6.2 summarizes the characteristics of the basic configuration which satisfy V_p > 2V_{min_in} criterion using a single supercapacitor and the two general configurations which satisfy V_p > 2V_{min_in} and V_p < 2V_{min_in} the criteria using an array of supercapacitors.

the efficiency improvement factor is a benchmark indication of this technique, and for the two different general cases discussed in Section 6.4, these are (1+ n) and (1+ 1/n) for the two cases of  V_p > 2V_{min_in} and V_p < 2V_{min_in}, respectively.

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6.6 SCALDO Implementation Examples

6.6.1 12-to-5 V SCALDO regulator

Fig.  6.13 shows the schematic implementation of the 12-to-5 V SCALDO regulator which satisfies the criteria, V_p > 2V_{min_in} , in the form of its basic configuration, n = 1. In designing this prototype, an LDO of the type MCP1827 from Microchip Technology Inc., which has the specifications shown in Table 6.4, was used as the main low dropout regulator. For higher-efficiency LDO operation, an approximate LDO input voltage of 0.3 V above the regulated output voltage (5 V) was chosen, so that V_{min_in} was maintained at 5.3 V. As the power supply input voltage was around 12 V and the regulated output is 5 V, three supercapacitors of 4 F/2.5 V of the type PC-series from Maxwell Technologies, were connected in series to maintain the required voltage level of the series dropper element. This resulted in 1.33 F/7.5 V resultant capacitor as the series capacitor.

Solid state relays of the type PVN012 from International Rectifier were used as S1, S2, S3, and S4 switches. Switches S1 and S3 control supercapacitor charging, while S2and S4 control the discharge phase. Solid state relays were used in this proof-of concept prototype to avoid complications arising from the body diode of common power MOSFETS. A PIC microcontroller of the type PIC16F684 was used as the controller to drive the photovoltaic switches. An independent 5 V regulator (LM7805) was used to power the microcontroller. The S1,S2, S3, and S4 switches were controlled through the RA0, RA5, RA1, and RA2 port pins of the microcontroller respectively. The LDO input voltage was monitored through the RA4 port pin. The voltage level at this pin is converted to digital format using 10-bit analog to digital converter of the PIC which operates at 4 MHz oscillation frequency. The result is then compared with reference point (digital value of the minimum LDO working voltage, V_{min_in}) and the switching between the supercapacitor charge and discharge phases was made accordingly. The microcontroller firmware was developed to drive the switches based on algorithm shown in the flow chart in Fig.  6.14.

A switch-over period, t_sw was designed to accommodate any transition delays of the PVN012 switches. This creates a short time duration just before the circuit is transferred from the supercapacitor charge mode to the discharge mode. Time duration is set by the PIC micro-controller according to the switch delay. The time duration is determined according to the data sheet of the switch and typically is about 300 ms. Fig.  6.15 shows the delay characteristics of the PVN012 switch.

To keep the linear regulator powered during the switch transitions, a buffer capacitor (C_B) with sufficient capacitance was connected in between the linear regulator input and the ground terminal. In t_sw time duration, the buffer capacitor is expected to discharge into the LDO input. The value of the buffer capacitor (C_B) can be determined as shown in the Eqn (6.26) using the maximum load current capability of the LDO (I_{max_L}), switching time delays of a PVN012 switch (t_sw) and the minimum possible input voltage at the LDO input (V_{min_in}). 1000 mF electrolytic capacitor was chosen as the C_B for the 12-to-5 V SCALDO design.