EE Product News

16-Bit ADC Teams With Low Jitter Clock

Claiming to deliver the highest SNR and SFDR and lowest jitter for communications, defense, and test and measurement applications, the ADS5483 16-bit, single-channel 135-Msamples/s a/d converter pairs with the CDCE72010 clock synthesizer to provide what the company describes as unmatched dynamic system-level performance. Reportedly the industry’s highest, the ADS5483 can achieve a SNR of 78.6 dB full scale with a 95-dBc SFDR for a 70-MHz input frequency. The device promises easier analog front-end designs by incorporating a fully differential input buffer. Additionally, it employs differential DDR LVDS outputs to reduce the number of I/O traces and pins it consumes on FPGA or ASIC devices. The CDCE72010 clock synthesizer specifies an additive jitter performance of less than 50 fs. The synthesizer accommodates a wide range of frequencies and can support up to 10 LVPECL, 10 LVDS, or 20 LVCMOS configurable outputs at frequencies up to 1.5 GHz and input frequencies from 8 kHz up to 500 MHz. Users can integrate two frequency sets within one clock synthesizer with the option of two external VCO/VCXOs. The device also integrates EEPROM to store default settings, eliminating the need for an external component. Available in QFN-64 PowerPAD packages, prices for the ADS5483 and CDCE72010 are $65 and $10.95 each/1,000, respectively. TEXAS INSTRUMENTS INC., Dallas, TX. (800) 477-8924.


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TAGS: Defense
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