Electronic Design

Acquire And Control Linear CCD Sensors Using EPP Protocol

A linear CCD camera is an essential component in many engineering and consumer applications. Usually, designers must contend with expensive commercial cameras supported with complex interfaces that can't be easily adapted for a wide range of applications. Described in this article is a simple and low-cost circuit that can control and acquire many commercial CCD sensors using an interface based on the Enhanced Parallel Port protocol (EPP-IEEE-1284 standard).

Most new-generation sensors, such as the ILX511 from the Sony family, can be driven using only two signals. The Sample Line signal SL (in our circuit, the FROG input signal to the CCD sensor) is used for line sampling, while the Phase Clock signal FCLK is used for charge shifting. All acquisition processes must be synchronized using these signals.

The idea is to generate SL and FCLK to drive the CCD sensor, and, simultaneously, use them for acquisition. The EPP protocol is well suited to this task, since this enables high-speed, full handshaking and is easily accessibly in today's PC architectures.

The circuit in Figure 1 consists of a linear CCD sensor, a flash analog-to-digital converter (the AD9280 from Analog Devices), a high-speed rail-to-rail amplifier (AD8041), and a timing generator constructed using six Schmitt inverters (74HC14s). The entire circuit is powered by a single 5-V supply.

The signal nWrite, generated in the "write" mode of the EPP (Fig. 2a), produces the SL signal by using U1D, U1E, D2, R2, and C2 to stretch out the nWrite pulse. On the other hand, the signal nDStrb generates the CCD_CLK and AD_CLK signals, which serve as pixel clocks for the shift (FCLK) operation and the analog-to-digital conversion (AD_CLK) simultaneously.

On the falling edge of the nDStrb signal, the analog CCD signal is sampled using the internal sample-and-hold circuit of the ILX511 (enabled using the SHSW pin) output on the VOUT pin. This signal is amplified and buffered by R7, R8, and U4A, and sampled on the rising edge of AD_CLK by the AD8041. The gates U1B and U1C with C1, R1, and D1 produce signal nWait. On the rising edge of nWait, the digital data from the analog-to-digital output on D0-D7 are strobed into PC memory.

Note that the sampling pixel period is directly proportional to the nDStrb period and can be adjusted by modifying the R1/C1 time constant. For the current implementation of the EPP protocol, the sampling pixel period is limited to a minimum of 0.5 µs.

From a software point of view, the operations described can be accomplished using only three lines of code:

outp(port+4,255);                    /* generate SL */
for( i = 0; i < MAX_N_OF_PIXELS; i++ ) /* read pixels */
a\[ i \]=inp(port+4 );

It's well known that the analog level of a CCD signal (for all pixels) is proportional to the line sampling (integration) time. Also, to achieve uniform performance, the sampling time must be constant (Fig. 2b). Using the polling method, this isn't possible because the period of the nWrite signal depends on the software flow. The hardware interrupt IRQ7 is easily accessed from the parallel port and can be used to solve this problem. Specifically, the oscillator built using U1F produces a line read strobe signal.

For this approach, the software routines above must be moved to the IRQ7 (0x0f) interrupt handler. Alternately, an appropriate software interrupt, such as the 0x1C (timer interrupt), can be used instead of IRQ7. Finally, to use this interface as a camera, all that's required is the addition of a lens to the CCD sensor.

One line of the scanned image obtained using this architecture is shown in Figure 3. The code listing details an interrupt-driven "C" program that supports it. The performance limits of the proposed circuit are: pixel rate = 2 Mbytes/s; line rate = 1000 lines/s; signal-to-noise ratio = 41.25 dB.

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