Analog-to-digital-converter (ADC) architectures vary greatly in their performance capabilities. ADC application needs are even more diverse. So it should come as no surprise that the development of ADC chips is moving simultaneously in multiple directions.
Chip developers are pushing their new designs to achieve a number of performance goals at varying levels. They're pursuing faster conversion rates, higher resolution, better noise performance, and lower power consumption. Much effort is put into shrinking the package and getting more channels of data conversion in a given package. Often, chip vendors look to integrate the ADC with related functions, such as voltage references or input amplifiers. Or, they may be investigating the best way to integrate ADCs with digital-to-analog converters (DACs) and other functions within the signal chain of a specific system. Although some of these parts enter data-converter catalogs as application-specific standard products, many are true ASICs.
With so many trends occurring simultaneously, vendors of monolithic ADCs can carve out many niches. What results is a wide array of converters optimized for different combinations of application requirements. For example, among high-speed ADCs—those with 10-Msample/s or faster performance—some parts may be optimized purely for speed, while others seek an optimum tradeoff of speed and power. Another factor, cost, counts heavily in many applications and naturally shapes many converter developments.
TOP TEN- THE SWITCH FROM PARALLEL to serial data interfaces is drastically reducing I/O requirements for DACs and ADCs. With fewer pins needed, newer data converters can move to smaller package outlines, or to combine more converter channels per chip. Precision data converters will continue to migrate to tiny surface-mount packages. Currently, 8- to 12-bit ADCs operating at 1 Msample/s are offered in the minuscule SC-70 package, while 14- and 16-bit ADCs with 100-ksample/s performance are available in the somewhat larger six-pin SOT-23s.
- LOW-VOLTAGE DIFFERENTIAL SIGNALING (LVDS) is becoming more popular as ADCs move to higher speeds. For converters with 12 bits or more of resolution, LVDS becomes critical at speeds of 100 Msamples/s or more to maintain the converters' dynamic performance. At that rate, the effect of noise generated by CMOS output drivers on ADC dynamic range becomes noticeable. However, demultiplexing of CMOS outputs can extend their performance to 200 Msamples/s or more. Parallel LVDS doubles the number of output pins versus standard CMOS outputs. Demultiplexed CMOS also requires twice as many pins (possibly more), though, when compared with standard CMOS.
- THE SERIAL FORM OF LVDS will become more popular in high-speed ADCs in the coming years. It offers the same benefits as parallel LVDS (better SINAD and SFDR, lower EMI) at higher speeds while reducing the number of output pins to just two. Serial LVDS also consumes less power.
- DYNAMIC RANGE REQUIREMENTS will slow migration to finer CMOS process geometries while encouraging development of new circuit architectures and multiple die solutions. In the past, data-converter designers could migrate their designs to finer process geometries and, without significant redesign, obtain higher performance, lower power, smaller size, and greater integration. However, at 0.25 µm and below, the move from one process to another gets more complicated as supply voltages fall with each move. At the analog interface, the lower voltage of the newer process may prevent sufficient dynamic range as required by the customer's application. To get to higher performance, some ADC developers will implement new architectures or co-package multiple die.
- SOME DEVELOPMENT OF EMBEDDED CONVERTERS is ongoing in 0.13-µm CMOS. But many high-performance ADCs will continue to be fabricated in less cutting-edge processes because of dynamic range and noise considerations. For example, many high-speed data converters are being developed on 0.18 µm, while a host of precision 12- to 16-bit data converters use 0.25-µm CMOS.
- SIGMA-DELTA CONVERTERS with 16-bit resolution may reach the 10-Msample/s limit this year, crossing over into high-speed territory. Devices now in production, such as Texas Instruments' ADS1605, are already at 5 Msamples/s.
- SPEEDY SAR CONVERTERS may approach the 10-Msample/s level that separates high-speed ADCs from general-purpose converters. Faster SARs will digitize more channels per chip in CT scanners, ATE, and other systems. Among the latest SARs, Analog Devices' AD7621 is a 16-bit, 3-Msample ADC with an INL and DNL of 1 LSB.
- PIPELINE CONVERTERS WILL EXTEND performance to provide faster conversion rates and higher resolutions. The applications that will benefit from these advances include wireless basestations, automatic test equipment, medical imaging (MRI), and various other imaging applications. Among recently introduced pipeline converters, Texas Instruments' ADS5500 extends 14-bit performance to 125 Msamples/s. The company plans to spin off multichannel versions of this 3.3-V powered converter.
- FASTER PIPELINE ADCs for IF sampling will eliminate a stage of downconversion in some broadband applications. In such applications, the change from two stages of frequency conversion to one reduces cost, power, and board-space requirements by eliminating a mixer, a frequency synthesizer, filter components, and drivers. One recently introduced ADC from Maxim Integrated Products achieves 10-bit, 250-Msample/s performance.
- CONVERTER VENDORS ARE INTRODUCING more device families rather than simply releasing individual ADCs. By providing pin-compatible converters with different options for speed or resolution, the vendors are giving system designers a migration path to upgrade their designs as more advanced ADCs emerge.